EP4CE55F29C8LN Altera, EP4CE55F29C8LN Datasheet - Page 352
EP4CE55F29C8LN
Manufacturer Part Number
EP4CE55F29C8LN
Description
IC CYCLONE IV FPGA 55K 780FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F29C8LN
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
374
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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1–72
Cyclone IV Device Handbook, Volume 2
1
Figure 1–69
Figure 1–69. Transceiver Configuration in SDI Mode
Altera recommends driving rx_bitslip port low in configuration where
low-latency PCS is not enabled. In SDI systems, the word alignment and framing
occurs after de-scrambling, which is implemented in the user logic. The word
alignment therefore is not useful, and keeping rx_bitslip port low avoids the word
aligner from inserting bits in the received data stream.
Functional Mode
Channel Bonding
Low-Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency (MHz)
Data Rate (Gbps)
shows the transceiver configuration in SDI mode.
HD - 1.4835/1.485
3G - 2.967/2.97
HD - 74.175/74.25
3G - 148.35/148.5
Disabled
Enabled
20-Bit
(7-bit, 10-Bit)
Disabled
Disabled
Disabled
Bit Slip
HD - 1.4835/1.485
HD - 74.175/74.25
Disabled
Disabled
10-Bit
Chapter 1: Cyclone IV Transceivers Architecture
×1 (HD or 3G)
SDI
HD - 1.4835/1.485
3G - 2.967/2.97
HD - 74.175/74.25
3G - 148.35/148.5
Disabled
Enabled
© December 2010 Altera Corporation
20-Bit
Transceiver Functional Modes
Disabled
Disabled
Disabled
Enabled
HD - 1.4835/1.485
HD - 74.175/74.25
Disabled
Disabled
10-Bit
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