EP3C10U256C6N Altera, EP3C10U256C6N Datasheet - Page 260
![IC CYCLONE III FPGA 10K 256-UBGA](/photos/6/73/67381/ep3c10u256c6n_sml.jpg)
EP3C10U256C6N
Manufacturer Part Number
EP3C10U256C6N
Description
IC CYCLONE III FPGA 10K 256-UBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10U256C6N.pdf
(274 pages)
Specifications of EP3C10U256C6N
Number Of Logic Elements/cells
10320
Number Of Labs/clbs
645
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-UBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
182
Frequency (max)
500MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
UFBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2433
EP3C10U256C6N
EP3C10U256C6N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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11–6
Software Support
Cyclone III Device Handbook, Volume 1
CRC calculation time depends on the device and the error detection clock frequency.
Table 11–6
maximum clock frequencies for Cyclone III device family.
Table 11–6. CRC Calculation Time
Enabling the CRC error detection feature in the Quartus II software generates the
CRC_ERROR output to the optional dual purpose CRC_ERROR pin.
To enable the error detection feature using CRC, perform the following steps:
1. Open the Quartus II software and load a project using Cyclone III device family.
2. On the Assignments menu, click Settings. The Settings dialog box appears.
3. In the Category list, select Device. The Device page appears.
4. Click Device and Pin Options, as shown in
5. In the Device and Pin Options dialog box, click the Error Detection CRC tab.
6. Turn on Enable error detection CRC.
7. In the Divide error check frequency by box, enter a valid divisor as documented
8. Click OK.
Cyclone III
Cyclone III LS
Notes to
(1) The minimum time corresponds to the maximum error detection clock frequency and may vary with different
(2) The maximum time corresponds to the minimum error detection clock frequency and may vary with different PVT.
in
1
processes, voltages, and temperatures (PVT).
Table 11–5 on page
Table
The divisor value divides down the frequency of the configuration
oscillator output clock. This output clock is used as the clock source for the
error detection process.
lists the estimated time for each CRC calculation with minimum and
11–6:
Device
11–5.
EP3CLS100
EP3CLS150
EP3CLS200
EP3CLS70
EP3C120
EP3C10
EP3C16
EP3C25
EP3C40
EP3C55
EP3C80
EP3C5
Chapter 11: SEU Mitigation in the Cyclone III Device Family
Minimum Time (ms)
Figure
(1)
15
23
31
45
42
42
79
79
5
5
7
9
11–2.
© December 2009 Altera Corporation
Maximum Time (s)
11.77
15.81
22.67
21.24
21.24
40.27
40.27
Software Support
2.29
2.29
3.17
4.51
7.48
(2)
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