EP3C10U256C6N Altera, EP3C10U256C6N Datasheet - Page 216
![IC CYCLONE III FPGA 10K 256-UBGA](/photos/6/73/67381/ep3c10u256c6n_sml.jpg)
EP3C10U256C6N
Manufacturer Part Number
EP3C10U256C6N
Description
IC CYCLONE III FPGA 10K 256-UBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10U256C6N.pdf
(274 pages)
Specifications of EP3C10U256C6N
Number Of Logic Elements/cells
10320
Number Of Labs/clbs
645
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-UBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
182
Frequency (max)
500MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
UFBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2433
EP3C10U256C6N
EP3C10U256C6N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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9–56
Cyclone III Device Handbook, Volume 1
f
1
After the first device completes configuration in a multi-device configuration chain,
its nCEO pin drives low to activate the nCE pin of the second device, which prompts
the second device to begin configuration. Therefore, if these devices are also in a JTAG
chain, ensure that the nCE pins are connected to GND during JTAG configuration or
that the devices are JTAG configured in the same order as the configuration chain. As
long as the devices are JTAG configured in the same order as the multi-device
configuration chain, the nCEO pin of the previous device drives the nCE pin of the
next device low when it has successfully been JTAG configured. You can place other
Altera devices that have JTAG support in the same JTAG chain for device
programming and configuration.
JTAG configuration allows an unlimited number of Cyclone III device family to be
cascaded in a JTAG chain.
For more information about configuring multiple Altera devices in the same
configuration chain, refer to the
volume 2 of the Configuration Handbook.
Figure 9–28
microprocessor.
Figure 9–28. JTAG Configuration of a Single Device Using a Microprocessor
Notes to
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
(2) Connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If you only use a
(3) The nCE pin must be connected to GND or driven low for successful JTAG configuration.
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. Signals driving into TDI, TMS, and TCK must fit the
chain.
JTAG configuration, connect the nCONFIG pin to logic high and the MSEL[3..0] pins to ground. In addition, pull
DCLK and DATA[0] either high or low, whichever is convenient on your board.
maximum overshoot equation outlined in
Figure
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
shows JTAG configuration of a Cyclone III device family with a
9–28:
Microprocessor
ADDR
Memory
DATA
Configuring Mixed Altera FPGA Chains
“Configuration and JTAG Pin I/O Requirements” on page
N.C.
(2)
(2)
(2)
Cyclone III Device Family
nCONFIG
DATA[0]
DCLK
TDI
TCK
TMS
nCEO
nCE
(4)
CONF_DONE
(4)
(3)
(4)
MSEL[3..0]
nSTATUS
TDO
V
© December 2009 Altera Corporation
(2)
CCIO
10 kΩ
(1)
V
CCIO
10 kΩ
(1)
Configuration Features
chapter in
9–7.
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