EP3C10U256C6N Altera, EP3C10U256C6N Datasheet - Page 115
![IC CYCLONE III FPGA 10K 256-UBGA](/photos/6/73/67381/ep3c10u256c6n_sml.jpg)
EP3C10U256C6N
Manufacturer Part Number
EP3C10U256C6N
Description
IC CYCLONE III FPGA 10K 256-UBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10U256C6N.pdf
(274 pages)
Specifications of EP3C10U256C6N
Number Of Logic Elements/cells
10320
Number Of Labs/clbs
645
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-UBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
182
Frequency (max)
500MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
UFBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2433
EP3C10U256C6N
EP3C10U256C6N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C10U256C6N PDF datasheet #6
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- Download datasheet (6Mb)
Chapter 6: I/O Features in the Cyclone III Device Family
Termination Scheme for I/O Standards
Figure 6–9. Cyclone III Device Family Differential SSTL I/O Standard Termination
Note to
(1) Only Differential SSTL-2 I/O standard supports Class II output.
© December 2009
Termination
Termination
On-Board
External
Figure
OCT
6–9:
Altera Corporation
Cyclone III Device
Family Series OCT
Transmitter
Transmitter
50
Figure 6–8. Cyclone III Device Family Differential HSTL I/O Standard Termination
Differential SSTL Class I
25
25
50
50
50
50
50
50
V TT
V TT
Termination
Termination
50
On-Board
50
External
V TT
OCT
V TT
Receiver
Receiver
Cyclone III Device
Family Series OCT
Transmitter
Transmitter
50
Cyclone III Device
Family Series OCT
Transmitter
Transmitter
25
Differential HSTL
V TT
V TT
50
V TT
25
25
Differential SSTL Class II
50
V TT V TT
(Note 1)
V TT
V TT
V TT
50
50
Cyclone III Device Handbook, Volume 1
50
50
50
50
Receiver
Receiver
50
50
V TT
V TT V TT
50
V TT
50
Receiver
Receiver
6–15
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