EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 47

• Manufacturer Part Number: EP3C16F484C8N
• Description: IC CYCLONE III FPGA 16K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16F484C8N

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 346
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 346
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 963
• Family Type: Cyclone III
• No. Of I/o's: 346
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2474

Verification
Figure 8. Early Timing Estimate
© November 2008 Altera Corporation
f
f
Checking Design Timing
To ensure that your design works, check the timing report to ensure that there is no
timing violation. It is important that the internal and I/O timings are met. The f
from the timing report indicates the maximum frequency at which your design can
operate. To ensure that the Cyclone III device interfaces correctly with other devices
on the board, check the t
when the Cyclone III device receives data from another device, make sure that the t
and t
register. Violating t
Metastable output can become incorrect for short durations, thus affecting the design
functionality.
When the Cyclone III device transmits registered data to another device, check the t
of the Cyclone III device to estimate the data arrival time for the external device.
For more information about the TimeQuest Timing Analyzer and the Classic Timing
Analyzer, refer to the
Timing Analyzer
For more information about metastability, refer to
Devices.
H
are not violated when the data is being clocked into the Cyclone III device
chapters, respectively, in volume 3 of the Quartus II Handbook.
SU
or t
Quartus II TimeQuest Timing Analyzer
SU
H
, t
can cause the register output to become metastable.
CO
, t
H
, and t
PD
values from the timing report. For example,
AN 42: Metastability in Altera
and the
Quartus II Classic
MAX
Page 47
CO
SU