EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 16
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Page 16
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The Logic Analyzer Interface requires JTAG connection and communicates with the
device through an Altera download cable. Additional LEs and I/Os are needed as
well.
For more information about ways to use the Logic Analyzer Interface feature for
debugging, refer to the
volume 3 of the Quartus II Handbook.
In-System Memory Content Editor
The In-System Memory Content Editor feature allows you to modify the content of
the memory or constant through the JTAG interface. This is useful in debugging for
design examples that perform read and write operation on the memory so that you
can check whether the design writes or reads the correct data to or from the memory.
Changes to the memory or constant can be done without interrupting the device's
functionality.
Specify that the memory or constant are modifiable when instantiating the
megafunction for the memory or constant. The In-System Memory Content Editor
requires JTAG connection and communicates with the device through an Altera
download cable. Additional LEs are needed when this feature is turned on.
For more information on ways to use the In-System Memory Content Editor to access
the on-chip memory, refer to the
in volume 3 of the Quartus II Handbook.
In-System Sources and Probes
This feature allows you to input simple virtual stimuli and capture the current value
of internal nodes in your design dynamically without the use of any external test
equipment. You can force trigger conditions set up using the SignalTap II Logic
Analyzer. The feature needs the altsource_probe megafunction instantiated in your
design before compilation and requires JTAG connection for the communication
through an Altera download cable. Additional LEs are needed when this feature is
used.
For more information on ways to use the In-System Source and Probes for debugging,
refer to the
the Quartus II Handbook.
Virtual JTAG Megafunction
Similar to the in-System Sources and Probes, the Virtual JTAG megafunction allows
you to apply virtual stimuli and capture the current value of internal nodes in your
design dynamically without the use of any external test equipment, albeit the Virtual
JTAG megafunction gives you a greater level of control but at the cost of greater
complexity. The feature needs the sld_virtual_jtag megafunction instantiated in your
design before compilation and requires JTAG connection for the communication
through an Altera download cable. Additional LEs are needed when this feature is
used.
For more information on ways to use the sld_virtual_jtag megafunction for
debugging, refer to the
Design Debugging Using In-System Sources and Probes
In-System Debugging Using External Logic Analyzers
sld_virtual_jtag Megafunction User
In-System Updating of Memory and Constants
Guide.
© November 2008 Altera Corporation
chapter in volume 3 of
Early System Planning
chapter in
chapter