EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 33

• Manufacturer Part Number: EP3C16F484C8N
• Description: IC CYCLONE III FPGA 16K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16F484C8N

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 346
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 346
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 963
• Family Type: Cyclone III
• No. Of I/o's: 346
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2474

Design and Compilation
© November 2008 Altera Corporation
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Clock Division
To obtain a lower frequency clock from a higher frequency clock, use a PLL to divide
the clock. PLL has a predictable output delay, and you can also change the phase of
the output signal to compensate for any delay. Using cascaded registers to divide the
clock introduces delay to the clock. As the ripple carry register chain propagates the
delay through the chain, there will be phase shift between the input clock and the
output clocks, and between different output clocks that are generated. Also, the delay
depends on the placement of the registers.
Inverted Clock
Use a PLL to generate an inverted clock, instead of using a NOT gate implemented
with an LE. The PLL allows you to set the phase shift of the output signal and
compensate for any delay between the input and output signals.
Multiplexed Clock
Some user designs require different clock source selection. Use the dedicated clock
control block or the PLL clock switchover feature of the Cyclone III device to
multiplex clock inputs. The clock control block allows up to four different clock source
selections, either from clock pins or PLL outputs as the source for the clock network.
You can dynamically select the clock source from two clock input pins and two PLL
outputs through the altclkctrl megafunction.
The PLL clock switchover feature also allows you to dynamically select between two
clock sources, either from clock input pins or output clocks from another PLL.
For more information about the Cyclone III clock control block and the PLL clock
switchover feature, refer to the
in volume 1 of the Cyclone III Device Handbook.
For information about how to use the altclkctrl megafunction for the clock control
block, refer to the
For information about how to use altpll megafunction for the Cyclone III PLL, refer to
the
Gated Clock
Gated clock allows users to turn off the clock signal. However, the recommended way
to turn off the clock in the Cyclone III device is to use the clock control block. The
clock control block allows you to power down the clock network. Use the altclkctrl
megafunction to instantiate the clock control block.
For more information about the Cyclone III clock control block, refer to the
Networks and PLLs in Cyclone III Devices
Handbook.
For information about how to use the clock control block, refer to the
Megafunction User Guide.
altpll Megafunction User Guide.
altclkctrl Megafunction User
Clock Networks and PLLs in Cyclone III Devices
chapter in volume 1 of the Cyclone III Device
Guide.
altclkctrl
Clock
chapter
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