EP2S180F1508C3 Altera, EP2S180F1508C3 Datasheet - Page 22
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EP2S180F1508C3
Manufacturer Part Number
EP2S180F1508C3
Description
IC STRATIX II FPGA 180K 1508FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S180F1508C3
Number Of Logic Elements/cells
179400
Number Of Labs/clbs
8970
Total Ram Bits
9383040
Number Of I /o
1170
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1508-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
179400
# I/os (max)
1170
Frequency (max)
778.82MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
179400
Ram Bits
9383040
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1508
Package Type
FC-FBGA
For Use With
544-1701 - DSP PRO KIT W/SII EP2S180N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2164
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S180F1508C3
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP2S180F1508C3N
Manufacturer:
ALTERA
Quantity:
624
Part Number:
EP2S180F1508C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Adaptive Logic Modules
Figure 2–10. Template for Supported Seven-Input Functions in Extended LUT Mode
Note to
(1)
2–14
Stratix II Device Handbook, Volume 1
If the seven-input function is unregistered, the unused eighth input is available for register packing. The second
register, reg1, is not available.
Figure
datae0
datae1
dataf0
dataf1
datac
dataa
datab
datad
(1)
2–10:
This input is available
for register packing.
Arithmetic Mode
The arithmetic mode is ideal for implementing adders, counters,
accumulators, wide parity functions, and comparators. An ALM in
arithmetic mode uses two sets of two four-input LUTs along with two
dedicated full adders. The dedicated adders allow the LUTs to be
available to perform pre-adder logic; therefore, each adder can add the
output of two four-input functions. The four LUTs share the dataa and
datab inputs. As shown in
adder0, and the carry-out from adder0 feeds to carry-in of adder1. The
carry-out from adder1 drives to adder0 of the next ALM in the LAB.
ALMs in arithmetic mode can drive out registered and/or unregistered
versions of the adder outputs.
5-Input
5-Input
LUT
LUT
combout0
Figure
2–11, the carry-in signal feeds to
D
reg0
Q
To general or
To general or
local routing
local routing
Altera Corporation
May 2007