EP2S180F1508C3 Altera, EP2S180F1508C3 Datasheet - Page 217
![IC STRATIX II FPGA 180K 1508FBGA](/photos/6/73/67335/544-stratix_ii_1508-fbga_sml.jpg)
EP2S180F1508C3
Manufacturer Part Number
EP2S180F1508C3
Description
IC STRATIX II FPGA 180K 1508FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S180F1508C3
Number Of Logic Elements/cells
179400
Number Of Labs/clbs
8970
Total Ram Bits
9383040
Number Of I /o
1170
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1508-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
179400
# I/os (max)
1170
Frequency (max)
778.82MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
179400
Ram Bits
9383040
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1508
Package Type
FC-FBGA
For Use With
544-1701 - DSP PRO KIT W/SII EP2S180N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2164
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S180F1508C3
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP2S180F1508C3N
Manufacturer:
ALTERA
Quantity:
624
Part Number:
EP2S180F1508C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
April 2011
Therefore, the DCD percentage for the 267 MHz SSTL-2 Class II
non-DDIO row output clock on a –3 device ranges from 47.5% to 52.5%.
Notes to
(1)
(2)
Column I/O Output
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL
Class I
1.8-V HSTL
Class II
1.5-V HSTL
Class I
1.5-V HSTL
Class II
1.2-V HSTL
LVPECL
Table 5–81. Maximum DCD for Non-DDIO Output on Column I/O
Pins
Standard I/O
Standard
The DCD specification is based on a no logic array noise condition.
1.2-V HSTL is only supported in -3 devices.
Table
Note (1)
(2)
5–81:
Maximum DCD for Non-DDIO Output
-3 Devices
190
140
125
185
105
100
170
80
90
70
80
80
85
50
55
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
-4 & -5 Devices
220
175
155
110
215
135
130
115
100
110
110
115
80
80
-
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
5–81