EP1AGX90EF1152I6N Altera, EP1AGX90EF1152I6N Datasheet - Page 98

• Manufacturer Part Number: EP1AGX90EF1152I6N
• Description: IC ARRIA GX FPGA 90K 1152FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX90EF1152I6N

• Number Of Logic Elements/cells: 90220
• Number Of Labs/clbs: 4511
• Total Ram Bits: 4477824
• Number Of I /o: 538
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2387

2–92
Open-Drain Output
Bus Hold
Arria GX Device Handbook, Volume 1
Table 2–24
Table 2–24. Programmable Drive Strength
Arria GX devices provide an optional open-drain (equivalent to an open collector)
output for each I/O pin. This open-drain output enables the device to provide
system-level control signals (for example, interrupt and write enable signals) that can
be asserted by any of several devices.
Each Arria GX device I/O pin provides an optional bus-hold feature. Bus-hold
circuitry can hold the signal on an I/O pin at its last-driven state. Because the
bus-hold feature holds the last-driven state of the pin until the next input signal is
present, an external pull-up or pull-down resistor is not needed to hold a signal level
when the bus is tri-stated.
Bus-hold circuitry also pulls undriven pins away from the input threshold voltage
where noise can cause unintended high-frequency switching. You can select this
feature individually for each I/O pin. The bus-hold output drives no higher than
V
programmable pull-up option cannot be used. Disable the bus-hold feature when the
I/O pin has been configured for differential signals.
Bus-hold circuitry uses a resistor with a nominal resistance (RBH) of approximately
7 k to pull the signal level to the last-driven state. This information is provided for
each V
going into user mode, the bus-hold circuit captures the value on the pin present at the
end of configuration.
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
Note to
(1) The Quartus II software default current setting is the maximum setting for each I/O standard.
CCIO
to prevent overdriving signals. If the bus-hold feature is enabled, the
CCIO
Table
I/O Standard
shows the possible settings for I/O standards with drive strength control.
voltage level. Bus-hold circuitry is active only after configuration. When
2–24:
I
Setting (mA) for Column
OH
24, 20, 16, 12, 8, 4
24, 20, 16, 12, 8, 4
/ I
12, 10, 8, 6, 4, 2
OL
12, 10, 8, 6, 4
12, 10, 8, 6, 4
12, 10, 8, 6, 4
20, 18, 16, 8
16, 12, 8, 4
24, 20, 16
20, 18, 16
20, 18, 16
Current Strength
8, 6, 4, 2
I/O Pins
12, 8
(Note 1)
I
Setting (mA) for Row I/O
OH
/ I
OL
12, 10, 8, 6, 4
© December 2009 Altera Corporation
Current Strength
10, 8, 6, 4
8, 6, 4, 2
12, 8, 4
12, 8, 4
8, 6, 4
Chapter 2: Arria GX Architecture
12, 8
Pins
8, 4
4, 2
16
—
—
—
I/O Structure