EP1AGX90EF1152I6N Altera, EP1AGX90EF1152I6N Datasheet - Page 114

• Manufacturer Part Number: EP1AGX90EF1152I6N
• Description: IC ARRIA GX FPGA 90K 1152FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX90EF1152I6N

• Number Of Logic Elements/cells: 90220
• Number Of Labs/clbs: 4511
• Total Ram Bits: 4477824
• Number Of I /o: 538
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2387

3–2
Table 3–1. Arria GX JTAG Instructions
Arria GX Device Handbook, Volume 1
SAMPLE/PRELOAD
EXTEST
BYPASS
USERCODE
IDCODE
HIGHZ
CLAMP
ICR instructions
PULSE_NCONFIG
CONFIG_IO
Notes to
(1) Bus hold and weak pull-up resistor features override the high-impedance state of
(2) For more information about using the
White Paper.
JTAG Instruction
Table
(1)
(1)
(1)
3–1:
(2)
Instruction Code
CONFIG_IO
00 0000 0101
00 0000 1111
11 1111 1111
00 0000 0111
00 0000 0110
00 0000 1011
00 0000 1010
00 0000 0001
00 0000 1101
—
instruction, refer to the
Allows a snapshot of signals at the device pins to be captured
and examined during normal device operation and permits an
initial data pattern to be output at the device pins. Also used by
the SignalTap II embedded logic analyzer.
Allows external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing
test results at the input pins.
Places the 1-bit bypass register between the
which allows the BST data to pass synchronously through
selected devices to adjacent devices during normal device
operation.
Selects the 32-bit
TDI
out of
Selects the
allowing
Places the 1-bit bypass register between the
which allows the BST data to pass synchronously through
selected devices to adjacent devices during normal device
operation, while tri-stating all of the I/O pins.
Places the 1-bit bypass register between the
which allows the BST data to pass synchronously through
selected devices to adjacent devices during normal device
operation while holding I/O pins to a state defined by the data in
the boundary-scan register.
Used when configuring an Arria GX device via the JTAG port with
a USB-Blaster
EthernetBlaster
using a .jam or .jbc via an embedded processor or JRunner
Emulates pulsing the nCONFIG pin low to trigger
reconfiguration even though the physical pin is unaffected.
Allows configuration of I/O standards through the JTAG chain for
JTAG testing. Can be executed before, during, or after
configuration. Stops configuration if executed during
configuration. Once issued, the CONFIG_IO instruction holds
nSTATUS low to reset the configuration device. nSTATUS is
held low until the IOE configuration register is loaded and the
TAP controller state machine transitions to the UPDATE_DR
state.
and
TDO
IDCODE
TDO
.
MorphIO: An I/O Reconfiguration Solution for Altera Devices
IDCODE
pins, allowing the
TM
HIGHZ
TM
, MasterBlaster
, or ByteBlaster II download cable, or when
to be serially shifted out of
USERCODE
register and places it between
,
CLAMP
IEEE Std. 1149.1 JTAG Boundary-Scan Support
Description
, and
register and places it between the
TM
USERCODE
© December 2009 Altera Corporation
Chapter 3: Configuration and Testing
, ByteBlasterMV
EXTEST
.
to be serially shifted
TDI
TDI
TDI
TDO
.
TM
and
and
and
TDI
,
TDO
TDO
TDO
and
pins,
pins,
pins,
TDO
TM
.
,