EP1AGX90EF1152I6N Altera, EP1AGX90EF1152I6N Datasheet - Page 140

• Manufacturer Part Number: EP1AGX90EF1152I6N
• Description: IC ARRIA GX FPGA 90K 1152FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX90EF1152I6N

• Number Of Logic Elements/cells: 90220
• Number Of Labs/clbs: 4511
• Total Ram Bits: 4477824
• Number Of I /o: 538
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2387

4–18
Table 4–21. 3.3-V LVDS I/O Specifications
Table 4–22. 3.3-V PCML Specifications
Table 4–23. LVPECL Specifications
Arria GX Device Handbook, Volume 1
V
V
V
V
V
R
Note to
(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V
V
V
V
V
V
V
V
V
R
R
V
V
V
V
V
R
Note to
(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V
CCIO
ID
ICM
OD
OCM
CCIO
ID
ICM
OD
OCM
T
CCIO
ID
ICM
OD
OCM
L
1
2
L
OD
OCM
Parameter
differential buffers are powered by VCC_PLL_OUT. For differential clock output/feedback operation, connect VCC_PLL_OUT to 3.3 V.
differential buffers are powered by VCC_PLL_OUT. For differential clock output/feedback operation, connect VCC_PLL_OUT to 3.3 V.
(1)
Symbol
Symbol
(1)
Table
Table
4–21:
4–23:
I/O supply voltage
Input differential voltage swing
(single-ended)
Input common mode voltage
Output differential voltage
(single-ended)
Output common mode voltage
Receiver differential input resistor
I/O supply voltage
Input differential voltage swing
(single-ended)
Input common mode voltage
Output differential voltage (single-ended)
Change in V
Output common mode voltage
Change in V
Output termination voltage
Output external pull-up resistors
Output external pull-up resistors
I/O supply voltage for top and bottom
PLL banks (9, 10, 11, and 12)
Input differential voltage swing
(single-ended)
Input common mode voltage
Output differential voltage (single-ended) R
Output common mode voltage
Receiver differential input discrete
resistor (external to Arria GX devices)
O D
O C M
Conditions
Parameter
Parameter
between high and low
between high and low
R
R
R
Minimum
L
L
Conditions
L
L
Minimum
= 100 
= 100 
= 100 
= 100 
—
—
—
—
3.135
300
300
1.5
2.5
—
—
—
—
—
—
—
45
45
Typical
3.135
1,650
300
525
1.0
90
Minimum
3.135
Typical
100
200
250
840
V
CCINT
90
CCINT
2.85
370
C C I O
Chapter 4: DC and Switching Characteristics
3.3
—
—
—
—
50
50
, not V
, not V
Maximum
© December 2009 Altera Corporation
600
100
3.3
—
—
—
CCIO
CCIO
Typical
1,250
350
100
3.3
—
—
. The PLL clock output/feedback
. The PLL clock output/feedback
Maximum
3.465
3.465
600
500
3.3
50
50
—
55
55
3.465
1,000
2,250
Units
970
110
2.5
Maximum
Operating Conditions
3.465
1,800
1,570
900
710
110
Parameter
Units
mV
mV
mV
mV


mV
mV
mV
V
V
V
V

V
V
Units
mV
mV
mV
mV

V