EP2SGX30DF780C5N Altera, EP2SGX30DF780C5N Datasheet - Page 65

• Manufacturer Part Number: EP2SGX30DF780C5N
• Description: IC STRATIX II GX 30K 780-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX30DF780C5N

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 361
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 780-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 33880
• # I/os (max): 361
• Frequency (max): 609.76MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 33880
• Ram Bits: 1369728
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1754

Altera Corporation
October 2007
Figure 2–42. Conditional Operation Example
The arithmetic mode also offers clock enable, counter enable,
synchronous up and down control, add and subtract control,
synchronous clear, synchronous load. The LAB local interconnect data
inputs generate the clock enable, counter enable, synchronous up and
down and add and subtract control signals. These control signals may be
used for the inputs that are shared between the four LUTs in the ALM.
The synchronous clear and synchronous load options are LAB-wide
signals that affect all registers in the LAB. The Quartus II software
automatically places any registers that are not used by the counter into
other LABs.
Carry Chain
syncdata
X[0]
X[1]
X[2]
Y[0]
Y[1]
Y[2]
ALM 1
ALM 2
Comb &
Comb &
Comb &
Comb &
Adder
Adder
Adder
Adder
Logic
Logic
Logic
Logic
X[2]
X[0]
X[1]
Adder output
is not used.
syncload
syncload
syncload
Stratix II GX Device Handbook, Volume 1
D
D
D
reg0
reg1
reg0
carry_out
Q
Q
Q
Stratix II GX Architecture
R[0]
R[1]
R[2]
To general or
local routing
To general or
local routing
To general or
local routing
To local routing &
then to LAB-wide
syncload
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