EP2SGX30DF780C5N Altera, EP2SGX30DF780C5N Datasheet - Page 138

IC STRATIX II GX 30K 780-FBGA

EP2SGX30DF780C5N

Manufacturer Part Number
EP2SGX30DF780C5N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX30DF780C5N

Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
609.76MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1754

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX30DF780C5N
Manufacturer:
ALTERA
0
Part Number:
EP2SGX30DF780C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
I/O Structure
2–130
Stratix II GX Device Handbook, Volume 1
Series termination without
calibration
Table 2–34. On-Chip Termination Support by I/O Banks (Part 1 of 2)
On-Chip Termination Support
On-Chip Termination
Stratix II GX devices provide differential (for the LVDS technology I/O
standard) and series on-chip termination to reduce reflections and
maintain signal integrity. On-chip termination simplifies board design by
minimizing the number of external termination resistors required.
Termination can be placed inside the package, eliminating small stubs
that can still lead to reflections.
Stratix II GX devices provide four types of termination:
Table 2–34
bank.
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVTTL
1.5-V LVCMOS
SSTL-2 class I and II
SSTL-18 class I
SSTL-18 class II
1.8-V HSTL class I
1.8-V HSTL class II
1.5-V HSTL class I
1.2-V HSTL
Differential termination (R
Series termination (R
Series termination (R
Parallel termination (R
I/O Standard Support
shows the Stratix II GX on-chip termination support per I/O
S
S
) without calibration
) with calibration
T
) with calibration
Top and Bottom Banks
D
)
(3, 4, 7, 8)
v
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v
v
v
v
v
v
Altera Corporation
Left Bank (1, 2)
October 2007
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