XC3S1400AN-4FGG676C Xilinx Inc, XC3S1400AN-4FGG676C Datasheet - Page 99
![IC SPARTAN-3AN FPGA 1400K 676FBG](/photos/6/73/67300/b-676_sml.jpg)
XC3S1400AN-4FGG676C
Manufacturer Part Number
XC3S1400AN-4FGG676C
Description
IC SPARTAN-3AN FPGA 1400K 676FBG
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3S50AN-4TQG144C.pdf
(2 pages)
3.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S1400AN-4FGG676C
Total Ram Bits
589824
Number Of Logic Elements/cells
25344
Number Of Labs/clbs
2816
Number Of I /o
502
Number Of Gates
1400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA
No. Of Logic Blocks
25344
No. Of Gates
1400000
No. Of Macrocells
25344
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
502
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1552
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1400AN-4FGG676C
Manufacturer:
XILINX
Quantity:
201
Company:
Part Number:
XC3S1400AN-4FGG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S1400AN-4FGG676C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
DS557 (v4.1) April 1, 2011
Product Specification
VCCINT
VCCINT
VCCO_2
VCCO_2
VREF_0
VREF_2
INPUT
INPUT
INPUT
INPUT
INPUT
L14P_0
L14N_0
L15P_0
L15N_0
L18P_2
L17N_2
L17P_2
GCLK4
GCLK5
GCLK2
GCLK1
GCLK0
GND
GND
GND
GND
11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCINT
VCCINT
VREF_2
INPUT
INPUT
INPUT
INPUT
L13N_0
L13P_0
L11N_0
L12P_0
L12N_0
L19N_2
L19P_2
L18N_2
L20N_2
L20P_2
GCLK3
CSI_B
GND
GND
GND
GND
MOSI
12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCAUX
VCCAUX
VCCO_0
VREF_0
INPUT
INPUT
INPUT
INPUT
INPUT
AWAKE
L11P_0
L10N_0
L09P_0
L09N_0
L31N_1
L19N_1
L15N_1
L23N_2
L23P_2
L22P_2
L22N_2
L21N_2
L21P_2
GND
GND
DOUT
13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCO_2
VREF_1
VREF_1
VREF_1
VREF_2
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
L07N_0
L07P_0
L10P_0
L39N_1
L35N_1
L31P_1
L23N_1
L19P_1
L15P_1
L04P_1
L25N_2
L25P_2
L24N_2
L24P_2
INIT_B
GND
14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D3
Bank 0
Bank 2
VREF_1
VREF_1
VREF_1
VREF_1
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
L08N_0
L08P_0
L06N_0
L06P_0
L03N_0
L39P_1
L35P_1
L27N_1
L23P_1
L16P_1
L11N_1
L12P_1
L04N_1
L27N_2
L27P_2
L26N_2
L26P_2
GND
GND
15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A8
A2
D1
D2
VCCAUX
Figure 22: FGG400 Package Footprint (Top View)
VCCO_0
VCCO_1
VCCO_1
L05N_0
L36N_1
INPUT
L24N_1
L16N_1
INPUT
L03N_1
L29N_2
L28N_2
L05P_0
L03P_0
L36P_1
L27P_1
L11P_1
L07P_1
L29P_2
L28P_2
GND
A21
16
I/O
I/O
I/O
I/O
I/O
A20
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A9
A1
RHCLK5
VCCO_2
VREF_0
VREF_0
L04N_0
L02N_0
L33N_1
L28N_1
L20N_1
L12N_1
L07N_1
L08N_1
L31N_2
L04P_0
L02P_0
L30P_1
L24P_1
L14P_1
L03P_1
L31P_2
L30P_2
GND
TDO
A18
17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A6
A3
A0
DIN/MISO
RHCLK4
RHCLK3
L01N_0
L34N_1
L30N_1
L25N_1
L22N_1
L18N_1
L14N_1
L02N_1
L30N_2
L01P_0
L33P_1
L28P_1
L20P_1
TRDY1
L13P_1
L10P_1
L08P_1
L05P_1
L32P_2
GND
GND
LDC0
A19
A13
A11
18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A7
A4
D0
www.xilinx.com
VCCO_1
VCCO_1
RHCLK2
RHCLK0
VCCO_1
L38N_1
L37N_1
L32N_1
L29N_1
L13N_1
DONE
L32N_2
L25P_1
L22P_1
L18P_1
L17P_1
L09P_1
L06P_1
L02P_1
GND
GND
CCLK
TCK
LDC1
A25
A23
A17
A12
A10
19
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A5
VCCAUX
RHCLK7
RHCLK6
RHCLK1
VREF_1
L26N_1
L21N_1
L17N_1
L09N_1
L05N_1
L06N_1
L01N_1
L38P_1
L37P_1
L34P_1
L32P_1
L29P_1
L26P_1
L21P_1
L10N_1
L01P_1
IRDY1
GND
GND
GND
LDC2
DS557_4_22_030911
HDC
A24
A22
A16
A15
A14
20
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
W
G
M
A
B
C
D
E
F
H
K
L
N
P
R
T
U
V
Y
J
Spartan-3AN FPGA Family: Pinout Descriptions
Right Half of FGG400
Package (Top View)
99