XC3S1400AN-4FGG676C Xilinx Inc, XC3S1400AN-4FGG676C Datasheet - Page 72
![IC SPARTAN-3AN FPGA 1400K 676FBG](/photos/6/73/67300/b-676_sml.jpg)
XC3S1400AN-4FGG676C
Manufacturer Part Number
XC3S1400AN-4FGG676C
Description
IC SPARTAN-3AN FPGA 1400K 676FBG
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3S50AN-4TQG144C.pdf
(2 pages)
3.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S1400AN-4FGG676C
Total Ram Bits
589824
Number Of Logic Elements/cells
25344
Number Of Labs/clbs
2816
Number Of I /o
502
Number Of Gates
1400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA
No. Of Logic Blocks
25344
No. Of Gates
1400000
No. Of Macrocells
25344
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
502
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1552
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
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Manufacturer:
XILINX
Quantity:
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Company:
Part Number:
XC3S1400AN-4FGG676C
Manufacturer:
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Quantity:
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Quantity:
20 000
Table 62: Types of Pins on Spartan-3AN FPGAs (Cont’d)
Package Pins by Type
Each package has three separate voltage supply inputs—VCCINT, VCCAUX, and VCCO—and a common ground return,
GND. The numbers of pins dedicated to these functions vary by package, as shown in
Table 63: Power and Ground Supply Pins by Package
A majority of package pins are user-defined I/O or input pins. However, the numbers and characteristics of these I/Os
depend on the device type and the package in which it is available, as shown in
number of single-ended I/O pins available, assuming that all I/O-, INPUT-, DUAL-, VREF-, and CLK-type pins are used as
general-purpose I/O. AWAKE is counted here as a dual-purpose I/O pin. Likewise, the table shows the maximum number of
differential pin-pairs available on the package. Finally, the table shows how the total maximum user-I/Os are distributed by
pin type, including the number of unconnected—N.C.—pins on the device.
Not all I/O standards are supported on all I/O banks. The left and right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2). Similarly, true differential output standards, such as LVDS,
RSDS, PPDS, miniLVDS, and TMDS, are only supported in the top or bottom banks (I/O banks 0 and 2). Inputs are
unrestricted. For more details, see the “Using I/O Resources” chapter in UG331.
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
TQG144
FTG256
FGG400
FGG484
FGG676
Color Code
Type with
Package
VCCAUX
CONFIG
VCCINT
MGMT
VCCO
JTAG
PWR
GND
# = I/O bank number, an integer between 0 and 3.
N.C.
Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every package has
two dedicated configuration pins. These pins are powered by VCCAUX. See UG332: Spartan-3
Generation Configuration User Guide for additional information on the DONE and PROG_B
signals.
Control and status pins for the power-saving Suspend mode. SUSPEND is a dedicated pin and
is powered by VCCAUX. AWAKE is a dual-purpose pin. Unless Suspend mode is enabled in the
application, AWAKE is available as a user-I/O pin.
Dedicated JTAG pin - 4 per device. Not available as a user-I/O pin. Every package has four
dedicated JTAG pins. These pins are powered by VCCAUX.
Dedicated ground pin. The number of GND pins depends on the package used. All must be
connected.
Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the package
used. The In-System Flash memory is powered by VCCAUX. All must be connected to +3.3V.
Dedicated internal core logic power supply pin. The number of VCCINT pins depends on the
package used. All must be connected to +1.2V.
Along with all the other VCCO pins in the same bank, this pin supplies power to the output buffers
within the I/O bank and sets the input threshold voltage for some I/O standards. All must be
connected.
This package pin is not connected in this specific device/package combination.
VCCINT
15
23
4
6
9
VCCAUX
10
14
4
4
8
VCCO
16
22
24
36
8
Description
GND
13
28
43
53
77
www.xilinx.com
Spartan-3AN FPGA Family: Pinout Descriptions
Table
64. The table shows the maximum
Table
63.
DONE, PROG_B
SUSPEND, AWAKE
TDI, TMS, TCK, TDO
GND
VCCAUX
VCCINT
VCCO_#
N.C.
Pin Name(s) in
Type
(1)
72