EP2C35F672C8N Altera, EP2C35F672C8N Datasheet - Page 20
![IC CYCLONE II FPGA 33K 672-FBGA](/photos/6/72/67268/ep2c35f672c8n_sml.jpg)
EP2C35F672C8N
Manufacturer Part Number
EP2C35F672C8N
Description
IC CYCLONE II FPGA 33K 672-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C35F672C8N
Number Of Logic Elements/cells
33216
Number Of Labs/clbs
2076
Total Ram Bits
483840
Number Of I /o
475
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
No. Of Logic Blocks
2076
Family Type
Cyclone II
No. Of I/o's
475
I/o Supply Voltage
3.3V
Operating Frequency Max
320MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
NANO-CYCLONE - KIT NANOBOARD AND CYCLONEII DC807-1002 - DAUGHTER CARD ALTERA CYCLONE IIP0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1692
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C35F672C8N
Manufacturer:
YAGEO
Quantity:
500 000
Company:
Part Number:
EP2C35F672C8N
Manufacturer:
ALTERA
Quantity:
500
Part Number:
EP2C35F672C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Logic Array Blocks
Figure 2–6. Direct Link Connection
2–8
Cyclone II Device Handbook, Volume 1
Direct link interconnect from
block, embedded multiplier,
left LAB, M4K memory
PLL, or IOE output
interconnect
Direct link
to left
Interconnect
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB
local interconnect is driven by column and row interconnects and LE
outputs within the same LAB. Neighboring LABs, PLLs, M4K RAM
blocks, and embedded multipliers from the left and right can also drive
an LAB’s local interconnect through the direct link connection. The direct
link connection feature minimizes the use of row and column
interconnects, providing higher performance and flexibility. Each LE can
drive 48 LEs through fast local and direct link interconnects.
shows the direct link connection.
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its LEs.
The control signals include:
■
■
■
■
■
Local
Two clocks
Two clock enables
Two asynchronous clears
One synchronous clear
One synchronous load
LAB
Direct link
interconnect
to right
Direct link interconnect from
right LAB, M4K memory
block, embedded multiplier,
PLL, or IOE output
Altera Corporation
February 2007
Figure 2–6