EP1K100QI208-2N Altera, EP1K100QI208-2N Datasheet - Page 16

• Manufacturer Part Number: EP1K100QI208-2N
• Description: IC ACEX 1K FPGA 100K 208-PQFP
• Manufacturer: Altera
• Series: ACEX-1K®r

Specifications of EP1K100QI208-2N

• Number Of Logic Elements/cells: 4992
• Number Of Labs/clbs: 624
• Total Ram Bits: 49152
• Number Of I /o: 147
• Number Of Gates: 257000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1826; EP1K100QI208-2N

ACEX 1K Programmable Logic Device Family Data Sheet
Figure 8. ACEX 1K Logic Element
16
Chip-Wide
labctrl1
labctrl2
labctrl3
labctrl4
data1
data2
data3
data4
Reset
Look-Up
The programmable flipflop in the LE can be configured for D, T, JK, or SR
operation. The clock, clear, and preset control signals on the flipflop can
be driven by global signals, general-purpose I/O pins, or any internal
logic. For combinatorial functions, the flipflop is bypassed and the LUT’s
output drives the LE’s output.
The LE has two outputs that drive the interconnect: one drives the local
interconnect, and the other drives either the row or column FastTrack
Interconnect routing structure. The two outputs can be controlled
independently. For example, the LUT can drive one output while the
register drives the other output. This feature, called register packing, can
improve LE utilization because the register and the LUT can be used for
unrelated functions.
The ACEX 1K architecture provides two types of dedicated high-speed
data paths that connect adjacent LEs without using local interconnect
paths: carry chains and cascade chains. The carry chain supports high-
speed counters and adders, and the cascade chain implements wide-input
functions with minimum delay. Carry and cascade chains connect all LEs
in a LAB and all LABs in the same row. Intensive use of carry and cascade
chains can reduce routing flexibility. Therefore, the use of these chains
should be limited to speed-critical portions of a design.
Preset
Clear/
Logic
Select
Clock
(LUT)
Table
Carry-Out
Carry-In
Chain
Carry
Cascade-Out
Cascade-In
Cascade
Chain
Register Bypass
D
ENA
CLRN
PRN
Q
Altera Corporation
Programmable
Register
To FastTrack
Interconnect
To LAB Local
Interconnect