EP1C12F256C7 Altera, EP1C12F256C7 Datasheet - Page 79

• Manufacturer Part Number: EP1C12F256C7
• Description: IC CYCLONE FPGA 12K LE 256-FBGA
• Manufacturer: Altera
• Series: Cyclone®r

Specifications of EP1C12F256C7

• Number Of Logic Elements/cells: 12060
• Number Of Labs/clbs: 1206
• Total Ram Bits: 239616
• Number Of I /o: 185
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1011

Timing Model
Altera Corporation
May 2008
Typically, the user-mode current during device operation is lower than
the power-up current in
Cyclone Power Calculator, available on the Altera web site, to estimate
the user-mode I
regulators based on the higher value.
The DirectDrive technology and MultiTrack interconnect ensure
predictable performance, accurate simulation, and accurate timing
analysis across all Cyclone device densities and speed grades. This
section describes and specifies the performance, internal, external, and
PLL timing specifications.
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
Preliminary and Final Timing
Timing models can have either preliminary or final status. The
Quartus
compilation if the timing models are preliminary.
status of the Cyclone device timing models.
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under
worst-case voltage and junction temperature conditions.
Table 4–18. Cyclone Device Timing Model Status
®
EP1C12
EP1C20
Device
EP1C3
EP1C4
EP1C6
II software issues an informational message during the design
CCINT
consumption and then select power supplies or
Table
4–17. Altera recommends using the
Preliminary
—
—
—
—
—
Table 4–18
Final
v
v
v
v
v
Timing Model
shows the
Preliminary
4–9