EP1C12F256C7 Altera, EP1C12F256C7 Datasheet - Page 56

IC CYCLONE FPGA 12K LE 256-FBGA

EP1C12F256C7

Manufacturer Part Number
EP1C12F256C7
Description
IC CYCLONE FPGA 12K LE 256-FBGA
Manufacturer
Altera
Series
Cyclone®r
Datasheet

Specifications of EP1C12F256C7

Number Of Logic Elements/cells
12060
Number Of Labs/clbs
1206
Total Ram Bits
239616
Number Of I /o
185
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1011

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Cyclone Device Handbook, Volume 1
2–50
Preliminary
of the standard. Using minimum settings provides signal slew rate
control to reduce system noise and signal overshoot.
possible settings for the I/O standards with drive strength control.
Open-Drain Output
Cyclone devices provide an optional open-drain (equivalent to an
open-collector) output for each I/O pin. This open-drain output enables
the device to provide system-level control signals (e.g., interrupt and
write-enable signals) that can be asserted by any of several devices.
Notes to
(1)
(2)
LVTTL (3.3 V)
LVCMOS (3.3 V)
LVTTL (2.5 V)
LVTTL (1.8 V)
LVCMOS (1.5 V)
Table 2–11. Programmable Drive Strength
SSTL-3 class I and II, SSTL-2 class I and II, and 3.3-V PCI I/O Standards do not
support programmable drive strength.
This is the default current strength setting in the Quartus II software.
Table
I/O Standard
2–11:
I
OH
/I
OL
Note (1)
Current Strength Setting (mA)
Table 2–11
24(2)
12(2)
16(2)
12(2)
8(2)
12
16
12
4
8
2
4
8
2
8
2
8
2
4
Altera Corporation
shows the
May 2008

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