EP1C12F256C7 Altera, EP1C12F256C7 Datasheet - Page 39

• Manufacturer Part Number: EP1C12F256C7
• Description: IC CYCLONE FPGA 12K LE 256-FBGA
• Manufacturer: Altera
• Series: Cyclone®r

Specifications of EP1C12F256C7

• Number Of Logic Elements/cells: 12060
• Number Of Labs/clbs: 1206
• Total Ram Bits: 239616
• Number Of I /o: 185
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1011

Figure 2–25. Cyclone PLL
Notes to
(1)
(2)
(3)
Altera Corporation
May 2008
LVDSCLK1p (2)
LVDSCLK1n (2)
The EP1C3 device in the 100-pin TQFP package does not support external outputs or LVDS inputs. The EP1C6
device in the 144-pin TQFP package does not support external output from PLL2.
LVDS input is supported via the secondary function of the dedicated clock pins. For PLL 1, the CLK0 pin’s secondary
function is LVDSCLK1p and the CLK1 pin’s secondary function is LVDSCLK1n. For PLL 2, the CLK2 pin’s secondary
function is LVDSCLK2p and the CLK3 pin’s secondary function is LVDSCLK2n.
PFD: phase frequency detector.
CLK0 or
CLK1 or
Figure
2–25:
Table 2–6
a Cyclone PLL.
Notes to
(1)
(2)
(3)
(4)
Note (1)
Clock multiplication and division
Phase shift
Programmable duty cycle
Number of internal clock outputs
Number of external clock outputs
Table 2–6. Cyclone PLL Features
÷n
The m counter ranges from 2 to 32. The n counter and the post-scale counters
range from 1 to 32.
The smallest phase shift is determined by the voltage-controlled oscillator (VCO)
period divided by 8.
For degree increments, Cyclone devices can shift all output frequencies in
increments of 45°. Smaller degree increments are possible depending on the
frequency and divide parameters.
The EP1C3 device in the 100-pin TQFP package does not support external clock
output. The EP1C6 device in the 144-pin TQFP package does not support external
clock output from PLL2.
Δt
Table
shows the PLL features in Cyclone devices.
PFD (3)
2–6:
Feature
Δt
Charge
Pump
÷m
Global Clock Network and Phase-Locked Loops
Loop
Filter
m/(n × post-scale counter)
Down to 125-ps increments (2),
Yes
2
One differential or one single-ended
VCO
Selectable at Each PLL
VCO Phase Selection
Output Port
PLL Support
Figure 2–25
Post-Scale
Counters
÷g0
÷g1
÷e
(1)
Preliminary
Global clock
Global clock
I/O buffer
(3)
shows
2–33
(4)