EP2C8Q208C8N Altera, EP2C8Q208C8N Datasheet - Page 20

• Manufacturer Part Number: EP2C8Q208C8N
• Description: IC CYCLONE II FPGA 8K 208-PQFP
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C8Q208C8N

• Number Of Logic Elements/cells: 8256
• Number Of Labs/clbs: 516
• Total Ram Bits: 165888
• Number Of I /o: 138
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 8256
• # I/os (max): 138
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 8256
• Ram Bits: 165888
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1671

Logic Array Blocks
Figure 2–6. Direct Link Connection
2–8
Cyclone II Device Handbook, Volume 1
Direct link interconnect from
block, embedded multiplier,
left LAB, M4K memory
PLL, or IOE output
interconnect
Direct link
to left
Interconnect
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB
local interconnect is driven by column and row interconnects and LE
outputs within the same LAB. Neighboring LABs, PLLs, M4K RAM
blocks, and embedded multipliers from the left and right can also drive
an LAB’s local interconnect through the direct link connection. The direct
link connection feature minimizes the use of row and column
interconnects, providing higher performance and flexibility. Each LE can
drive 48 LEs through fast local and direct link interconnects.
shows the direct link connection.
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its LEs.
The control signals include:
■
■
■
■
■
Local
Two clocks
Two clock enables
Two asynchronous clears
One synchronous clear
One synchronous load
LAB
Direct link
interconnect
to right
Direct link interconnect from
right LAB, M4K memory
block, embedded multiplier,
PLL, or IOE output
Altera Corporation
February 2007
Figure 2–6