EP2C5T144I8 Altera, EP2C5T144I8 Datasheet - Page 155
![IC CYCLONE II FPGA 5K 144-TQFP](/photos/6/70/67061/544-144-tqfp_sml.jpg)
EP2C5T144I8
Manufacturer Part Number
EP2C5T144I8
Description
IC CYCLONE II FPGA 5K 144-TQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C5T144I8
Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
89
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-2138
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C5T144I8
Manufacturer:
ALTERA
Quantity:
2
Company:
Part Number:
EP2C5T144I8N
Manufacturer:
ALTERA41
Quantity:
710
Part Number:
EP2C5T144I8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
February 2008
Notes to
(1)
(2)
t
t
t
t
t
t
t
t
t
t
t
t
t
J C P
J C H
J C L
J P S U
J P H
J P C O
J P Z X
J P X Z
J S S U
J S H
J S C O
J S Z X
J S X Z
Table 5–53. Cyclone II JTAG Timing Parameters and Values
Symbol
This information is preliminary.
This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For
1.8-V LVTTL/LVCMOS and 1.5-V LVCMOS, the JTAG port and capture register clock setup time is 3 ns and port
clock to output time is 15 ns.
Table
TCK
TCK
TCK
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
5–53:
f
clock period
clock high time
clock low time
Table 5–53
devices.
1
For more information on JTAG, refer to the
Boundary-Scan Testing for Cyclone II Devices
Handbook.
Parameter
(2)
(2)
Cyclone II devices must be within the first 17 devices in a JTAG
chain. All of these devices have the same JTAG controller. If any
of the Cyclone II devices are in the 18th position or after they will
fail configuration. This does not affect the SignalTap
analyzer.
(2)
shows the JTAG timing parameters and values for Cyclone II
(2)
(2)
DC Characteristics and Timing Specifications
Min
Cyclone II Device Handbook, Volume 1
20
20
10
10
—
—
—
—
—
—
40
5
5
chapter in the Cyclone II
IEEE 1149.1 (JTAG)
Max
13
13
13
25
25
25
—
—
—
—
—
—
—
®
II logic
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5–65