EP2C5T144I8 Altera, EP2C5T144I8 Datasheet - Page 108
![IC CYCLONE II FPGA 5K 144-TQFP](/photos/6/70/67061/544-144-tqfp_sml.jpg)
EP2C5T144I8
Manufacturer Part Number
EP2C5T144I8
Description
IC CYCLONE II FPGA 5K 144-TQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C5T144I8
Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
89
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-2138
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C5T144I8
Manufacturer:
ALTERA
Quantity:
2
Company:
Part Number:
EP2C5T144I8N
Manufacturer:
ALTERA41
Quantity:
710
Part Number:
EP2C5T144I8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Timing Specifications
5–18
Cyclone II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Larger
Designs
TSU
TH
TCO
TCLR
Table 5–15. Cyclone II Performance (Part 4 of 4)
Table 5–16. LE_FF Internal Timing Microparameters (Part 1 of 2)
Parameter
This application uses registered inputs and outputs.
This application uses registered multiplier input and output stages within the DSP block.
This application uses the same clock source for both A and B ports.
This application uses independent clock sources for A and B ports.
This application uses PLL clock outputs that are globally routed to connect and drive M4K clock ports. Use of
non-PLL clock sources or local routing to drive M4K clock ports may result in lower performance numbers than
shown here. Refer to the Quartus II timing report for actual performance numbers.
These numbers are for commercial devices.
These numbers are for automotive devices.
Table 5–15
8-bit, 1024 pt, Quad Output,
4 Parallel FFT Engines, Buffered
Burst, 3 Mults/5 Adders FFT
function
8-bit, 1024 pt, Quad Output,
4 Parallel FFT Engines, Buffered
Burst, 4 Mults/2 Adders FFT
function
Applications
:
–6 Speed Grade
Min
–36
266
141
191
—
—
—
—
Internal Timing
Refer to
Max
250
Tables 5–16
—
—
—
—
—
—
—
(1)
8053
7453
LEs
Resources Used
–7 Speed Grade
Min
through
–40
–38
306
286
135
141
244
217
Memory
Blocks
M4K
60
60
5–19
Blocks
Max
DSP
277
36
48
—
—
—
—
—
—
—
for the internal timing parameters.
(2)
Speed
Grade
200.0
200.0
–6
–8 Speed Grade
Min
–40
–40
306
306
135
141
244
244
Performance (MHz)
Speed
Grade
195.0
195.0
(6)
–7
Altera Corporation
149.23
151.28
Speed
Max
Grade
304
—
—
—
—
—
—
—
February 2008
(7)
–7
(3)
163.02
163.02
Speed
Grade
Unit
–8
ps
ps
ps
ps
ps
ps
ps
ps