EP1C3T100I7N Altera, EP1C3T100I7N Datasheet - Page 91
![IC CYCLONE FPGA 2910 LE 100-TQFP](/photos/6/70/67055/544-100-tqfp_sml.jpg)
EP1C3T100I7N
Manufacturer Part Number
EP1C3T100I7N
Description
IC CYCLONE FPGA 2910 LE 100-TQFP
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C3T100I7N
Number Of Logic Elements/cells
2910
Number Of Labs/clbs
291
Total Ram Bits
59904
Number Of I /o
65
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
100-TQFP, 100-VQFP
Family Name
Cyclone®
Number Of Logic Blocks/elements
2910
# I/os (max)
65
Frequency (max)
320.1MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
2910
Ram Bits
59904
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1663
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C3T100I7N
Manufacturer:
ALTERA42
Quantity:
735
Part Number:
EP1C3T100I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1C3T100I7NL
Manufacturer:
PHI
Quantity:
6 219
Altera Corporation
May 2008
LVCMOS
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
Table 4–40. Cyclone I/O Standard Column Pin Input Delay Adders (Part 1 of 2)
I/O Standard
External I/O Delay Parameters
External I/O delay timing parameters for I/O standard input and output
adders and programmable input and output delays are specified by
speed grade independent of device density.
Tables 4–40
and row I/O pins for all packages. If an I/O standard is selected other
than LVTTL 4 mA with a fast slew rate, add the selected delay to the
external t
4–28.
t
t
t
t
t
t
t
t
t
t
I N S U
I N H
O U T C O
X Z
Z X
I N S U P L L
I N H P L L
O U T C O P L L
X Z P L L
Z X P L L
Table 4–39. EP1C20 Row Pin Global Clock External I/O Timing Parameters
-6 Speed Grade
Min
Symbol
—
—
—
—
—
—
—
—
CO
through
–250
–250
–278
and t
Max
182
278
27
-6 Speed Grade
2.417
0.000
2.000
1.417
0.000
0.500
0
0
Min
—
—
—
—
SU
I/O parameters shown in
4–45
3.724
3.645
3.645
1.667
1.588
1.588
Max
-7 Speed Grade
Min
—
—
—
—
—
—
—
—
—
—
—
—
show the adder delays associated with column
-7 Speed Grade
2.779
0.000
2.000
1.629
0.000
0.500
Min
—
—
—
—
–288
–288
–320
Max
209
319
31
0
0
4.282
4.191
4.191
1.917
1.826
1.826
Max
—
—
—
—
-8 Speed Grade
Min
Tables 4–25
—
—
—
—
—
—
—
—
-8 Speed Grade
3.140
0.000
2.000
1.840
0.000
0.500
Min
—
—
—
—
–325
–325
–362
Max
236
361
35
0
0
through
4.843
4.740
4.740
2.169
2.066
2.066
Max
Timing Model
—
—
—
—
Preliminary
Unit
ps
ps
ps
ps
ps
ps
ps
ps
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4–21