EP1C3T100I7N Altera, EP1C3T100I7N Datasheet - Page 60
![IC CYCLONE FPGA 2910 LE 100-TQFP](/photos/6/70/67055/544-100-tqfp_sml.jpg)
EP1C3T100I7N
Manufacturer Part Number
EP1C3T100I7N
Description
IC CYCLONE FPGA 2910 LE 100-TQFP
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C3T100I7N
Number Of Logic Elements/cells
2910
Number Of Labs/clbs
291
Total Ram Bits
59904
Number Of I /o
65
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
100-TQFP, 100-VQFP
Family Name
Cyclone®
Number Of Logic Blocks/elements
2910
# I/os (max)
65
Frequency (max)
320.1MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
2910
Ram Bits
59904
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1663
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C3T100I7N
Manufacturer:
ALTERA42
Quantity:
735
Part Number:
EP1C3T100I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1C3T100I7NL
Manufacturer:
PHI
Quantity:
6 219
Cyclone Device Handbook, Volume 1
2–54
Preliminary
Each I/O bank can support multiple standards with the same V
input and output pins. For example, when V
support LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.
LVDS I/O Pins
A subset of pins in all four I/O banks supports LVDS interfacing. These
dual-purpose LVDS pins require an external-resistor network at the
transmitter channels in addition to 100-Ω termination resistors on
receiver channels. These pins do not contain dedicated serialization or
deserialization circuitry; therefore, internal logic performs serialization
and deserialization functions.
Table 2–13
device density.
MultiVolt I/O Interface
The Cyclone architecture supports the MultiVolt I/O interface feature,
which allows Cyclone devices in all packages to interface with systems of
different supply voltages. The devices have one set of V
internal operation and input buffers (V
output drivers (V
Note to
(1)
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
Table 2–13. Cyclone Device LVDS Channels
EP1C3 devices in the 100-pin TQFP package do not support the LVDS I/O
standard.
Device
Table
shows the total number of supported LVDS channels per
2–13:
CCIO
).
Pin Count
100
144
324
400
144
240
256
240
256
324
324
400
CCINT
), and four sets for I/O
Number of LVDS Channels
CCIO
is 3.3-V, a bank can
Altera Corporation
103
129
103
129
(1)
34
29
72
72
66
72
95
CC
pins for
May 2008
CCIO
for