DSPB56725AF Freescale Semiconductor, DSPB56725AF Datasheet - Page 7

• Manufacturer Part Number: DSPB56725AF
• Description: DSP 24BIT AUD 250MHZ 80-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56725AF

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 250MHz
• Non-volatile Memory: External
• On-chip Ram: 112kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Processor Series: DSP567xx
• Core: 56300
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

For correct operation of the internal power-on reset logic, the Core_VDD ramp rate (Tr) to full supply must be less than 10 ms,
as shown in
1.1.4
Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are
described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is charging and
discharging the capacitances of the pins and internal nodes.
Current consumption is described by the following formula:
The maximum internal current (I
operation conditions, which is not necessarily a real application case. The typical internal current (I
average switching of the internal buses on typical operating conditions.
For applications that require very low current consumption, do the following:
One way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board
effects (for example, to compensate for measured board current not caused by the DSP). Use the test algorithm, specific test
current measurements, and the following equation to derive the current per MIPS value.
Freescale Semiconductor
•
•
For a GPIO address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 150 MHz clock, toggling at
its maximum possible rate (75 MHz), the current consumption is
where
Minimize the number of pins that are switching.
Minimize the capacitive load on the pins.
where :
Figure
Figure 5. Ensure Correct Operation of Power-On Reset with Fast Ramp of Core_VDD
Power Consumption Considerations
4.
C=node/pin capacitance
V=voltage swing
f=frequency of node/pin toggle
I
I
F2=high frequency (any specified operating frequency)
F1=low frequency (any specified operating frequency lower than F2)
typF2
typF1
Symphony
=current at F2
=current at F1
Core_VDD
CCI
max) value reflects the typical possible switching of the internal buses on best-case
I/MIPS = I/MHz = (I
™
Example 1. Power Consumption Example
DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
I
=
0 V
50
x
10 12
I
=
–
C
×
x
typF2
3.3
V
×
x
Tr must be < 10 ms
75
- I
f
typF1
x
10 6
)/(F2 - F1)
Tr
=
12.375mA
1.0 V
CCItyp
) value reflects the
Eqn. 2
Eqn. 1
Eqn. 3
7