DSPB56725AF Freescale Semiconductor, DSPB56725AF Datasheet - Page 46

• Manufacturer Part Number: DSPB56725AF
• Description: DSP 24BIT AUD 250MHZ 80-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56725AF

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 250MHz
• Non-volatile Memory: External
• On-chip Ram: 112kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Processor Series: DSP567xx
• Core: 56300
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5
Table 21
properly with the part. Documentation is available from a local Freescale Semiconductor, Inc. (formerly Motorola) distributor,
semiconductor sales office, Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source
for the latest information).
6
Table 22
46
DSP56300 Family Manual
DSP56724/DSP56725 Reference Manual Detailed description of memory, peripherals, and interfaces
DSP56724 Product Brief
DSP56725 Product Brief
DSP56724/DSP56725 Data Sheet
Revision
2
1
0
lists the documents that provide a complete description of the DSP56724/DSP56725 devices and are required to design
summarizes revisions to this document.
Product Documentation
Revision History
Document Name
12/2008
3/2009
6/2008
Date
Symphony
Table 21. DSP56724 / DSP56725 Documentation
™
• Added
• In
• In
• Modified values and removed rows in
• Removed “IO_VDD_25” from
• In
• In
• In
• In
• Removed Section 1.2.5, “Timer Timing.”
• In
• In
• In
• In
• Initial public release.
DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
27, 33, 34, and 39. Removed 40 and renumbered subsequent items accordingly.
Updated
IO_VDD Before Core_VDD.”
12, and for No. 16, changed 4 to 7.
to 1000 and 300; in addition, updated the values for note 1.
No. 83, changed 20 to 15; for No. 86, changed 18 to 25; for No. 87, changed 21 to 25.
“LSYNC_IN (except LGTA/LUPWAIT),” changed 2 to 3.
“LCLK to output high impedance for LAD [23:0],” changed 9 to 8.1.
LCLK to output high impedance for LAD [23:0],” changed 19 to 17.1
DSPB56725CAF, and changed “DSPA56724AG” to “DSPB56724AG.”
Table
Table
Table 9,
Table 11,
Table
Table
Table
Table
Table
Table
Detailed description of the 56300-family architecture and the 24-bit
core processor and instruction set
Brief description of the DSP56724 device
Brief description of the DSP56725 device
(this document)
Electrical and timing specifications; pin and package descriptions
Section 1.1.4, “Power Consumption
Table 22. Revision History
7, “Reset, Stop, Mode Select, and Interrupt Timing,” for No. 15, changed 10 to
10, “SHI I2C Protocol Timing,” added note 7 and changed Max values for No. 50
11, “Enhanced Serial Audio Interface Timing,” for No. 82, changed 19 to 15; for
9, “Serial Host Interface SPI Protocol Timing,” updated values.
16, “EMC Timing Parameters (EMC PLL Enabled; LCRR[CLKDIV] = 2),” for
17, “EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 4),” for
18, “EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8),” for
19, “Ordering Information,” added rows for DSPB56724CAG and
Figure 12
“Serial Host Interface SPI Protocol Timing,” updated values for Nos. 24, 25,
“Enhanced Serial Audio Interface Timing,” for No. 71 changed 12.0 to 0.
and
Figure 13
Figure
Description
to reflect renumbering.
Description
4, “Prevent High Current Conditions by Applying
Table
Considerations.”
4, “DC Electrical Characteristics.”
Freescale Semiconductor
Order Number
DSP56300FM
DSP56724RM
DSP56724
DSP56724PB
DSP56725PB