DSPB56725AF Freescale Semiconductor, DSPB56725AF Datasheet - Page 12

• Manufacturer Part Number: DSPB56725AF
• Description: DSP 24BIT AUD 250MHZ 80-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56725AF

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 250MHz
• Non-volatile Memory: External
• On-chip Ram: 112kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Processor Series: DSP567xx
• Core: 56300
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12
Note:
1. When using fast interrupts and when IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply
2. For PLL disable, if using an external clock (PCTL Bit 13 = 1), no stabilization delay is required and recovery time will be defined
3. Periodically sampled and not 100% tested.
4. RESET duration is measured during the time in which RESET is asserted, V
No.
to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when using
fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
by the OMR Bit 6 settings.
For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shut down during Stop. Recovering from Stop requires the PLL
to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 200 us.
valid. When V
device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should
minimize this state to the shortest possible duration.
19
20
21
22
Duration of level sensitive IRQA assertion to ensure interrupt
service (when exiting Stop)
Interrupt Requests Rate
DMA Requests Rate
• PLL is active during Stop and Stop delay is enabled (OMR Bit
• PLL is active during Stop and Stop delay is not enabled (OMR
• PLL is not active during Stop and Stop delay is enabled (OMR
• PLL is not active during Stop and Stop delay is not enabled
• Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
• ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1, Timer, Timer_1
• DMA
• IRQ, NMI (edge trigger)
• IRQ (level trigger)
• Data read from ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1
• Data write to ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1
• Timer, Timer_1
• IRQ, NMI (edge trigger)
6 = 0)
Bit 6 = 1)
Bit 6 = 0)
(OMR Bit 6 = 1)
general-purpose transfer output valid caused by first interrupt
instruction execution
DD
is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the
Table 7. Reset, Stop, Mode Select, and Interrupt Timing (Continued)
Symphony
1
Characteristics
1
1, 2, 3
™
DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
(128KxT
(25 × T
(128 Kbytes × T
DD
10 × T
Expression
is valid, and the EXTAL input is active and
25 × T
12 × T
12 × T
C
8 × T
8 × T
6 × T
7 × T
2 × T
3 × T
C
) + PLL
) + PLL
C
+ 3.8
C
C
C
C
C
C
C
C
C
LOCK
LOCK
C)
Freescale Semiconductor
Min
655
125
855
200
—
—
—
—
—
—
—
—
—
Max
53.8
60.0
40.0
40.0
60.0
30.0
35.0
10.0
15.0
—
—
—
—
Unit
μs
ns
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns