DSPB56364AF100 Freescale Semiconductor, DSPB56364AF100 Datasheet - Page 35

• Manufacturer Part Number: DSPB56364AF100
• Description: IC DSP 24BIT AUD 100MHZ 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56364AF100

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (24 kB)
• On-chip Ram: 11.25kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
2
3
4
5
6
Freescale Semiconductor
152
153
154
155
156
No.
The number of wait states for Page mode access is specified in the DCR.
The refresh period is specified in the DCR.
All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t
read-after-read or write-after-write sequences).
Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state (See
BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page
access.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)
Last RD assertion to RAS deassertion
RD assertion to data valid
RD deassertion to data not valid
WR assertion to data active
WR deassertion to data high
impedance
Characteristics
6
DSP56364 Technical Data, Rev. 4.1
Symbol
t
ROH
t
t
GA
GZ
0.75 × T
1.5 × T
Expression
0.25 × T
T
C
− 7.5
C
C
− 4.0
− 0.3
C
External Memory Expansion Port (Port A)
71.0
37.2
Min
0.0
—
—
20 MHz
Figure 3-14
Max
42.5
12.5
OFF
4
—
—
—
and not t
1, 2, 3
24.7
46.0
Min
0.0
.).
—
—
30 MHz
PC
GZ
(continued)
.
equals 2 × TC for
Max
25.8
8.3
4
—
—
—
Unit
ns
ns
ns
ns
ns
3-19