DSPB56364AF100 Freescale Semiconductor, DSPB56364AF100 Datasheet - Page 12
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DSPB56364AF100
Manufacturer Part Number
DSPB56364AF100
Description
IC DSP 24BIT AUD 100MHZ 100-LQFP
Manufacturer
Freescale Semiconductor
Series
Symphony™r
Type
Audio Processorr
Datasheet
1.DSPB56364AF100.pdf
(148 pages)
Specifications of DSPB56364AF100
Interface
Host Interface, I²C, SAI, SPI
Clock Rate
100MHz
Non-volatile Memory
ROM (24 kB)
On-chip Ram
11.25kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Serial Host Interface
2-8
Signal
HREQ
Name
HA0
HA2
SS
Input or
Signal
Output
Type
Input
Input
Input
State During
Tri-stated
Tri-stated
Reset
Input
Input
Table 2-9 Serial Host Interface Signals (continued)
I
I
slave device address. HA0 is ignored when configured for the I
This signal is tri-stated during hardware, software, and individual reset. Thus, there is
no need for an external pull-up in this state.
This input is 5 V tolerant.
SPI Slave Select—This signal is an active low Schmitt-trigger input when configured
for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable
the SPI slave for transfer. When configured for the SPI master mode, this signal should
be kept deasserted (pulled high). If it is asserted while configured as SPI master, a bus
error condition is flagged. If SS is deasserted, the SHI ignores SCK clocks and keeps
the MISO output signal in the high-impedance state.
I
I
slave device address. HA2 is ignored in the I
This signal is tri-stated during hardware, software, and individual reset. Thus, there is
no need for an external pull-up in this state.
This input is 5 V tolerant.
Host Request—This signal is an active low Schmitt-trigger input when configured for
the master mode but an active low output when configured for the slave mode.
When configured for the slave mode, HREQ is asserted to indicate that the SHI is ready
for the next data word transfer and deasserted at the first clock pulse of the new data
word transfer. When configured for the master mode, HREQ is an input. When asserted
by the external slave device, it will trigger the start of the data word transfer by the
master. After finishing the data word transfer, the master will await the next assertion of
HREQ to proceed to the next transfer.
This signal is tri-stated during hardware, software, personal reset, or when the
HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for external pull-up in
this state.
This input is 5 V tolerant.
2
2
2
2
C Slave Address 0—This signal uses a Schmitt-trigger input when configured for the
C mode. When configured for I
C Slave Address 2—This signal uses a Schmitt-trigger input when configured for the
C mode. When configured for the I
DSP56364 Technical Data, Rev. 4.1
2
Signal Description
C slave mode, the HA0 signal is used to form the
2
C Slave mode, the HA2 signal is used to form the
2
C master mode.
Freescale Semiconductor
2
C master mode.