EPM9560ARC208-10 Altera, EPM9560ARC208-10 Datasheet - Page 21

• Manufacturer Part Number: EPM9560ARC208-10
• Description: IC MAX 9000 CPLD 560 208-RQFP
• Manufacturer: Altera
• Series: MAX® 9000r

Specifications of EPM9560ARC208-10

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 35
• Number Of Macrocells: 560
• Number Of Gates: 12000
• Number Of I /o: 153
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-RQFP
• Voltage: 3.3V/5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 35
• Family Name: MAX 9000
• # Macrocells: 560
• Number Of Usable Gates: 12000
• Frequency (max): 144.9MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 35
• # I/os (max): 153
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: RQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2363

Altera Corporation
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 9000 Device
The time required to program a single MAX 9000 device in-system can be
calculated from the following formula:
where: t
The ISP times for a stand-alone verification of a single MAX 9000 device
can be calculated from the following formula:
where: t
t
t
PR OG
VER
=
=
t
VPULSE
t
Cycle
f
t
Cycle
TCK
t
PROG
PPULSE
VER
VPULSE
PP ULSE
PTCK
VTCK
+
+
C ycle
--------------------------------
MAX 9000 Programmable Logic Device Family Data Sheet
Cyc le
------------------------------- -
= Programming time
= Sum of the fixed times to erase, program, and
= Number of TCK cycles to program a device
= TCK frequency
f
= Verify time
= Sum of the fixed times to verify the EEPROM cells
= Number of TCK cycles to verify a device
TC K
f
T CK
VTC K
verify the EEPROM cells
PTC K
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