EPM570GT100C5N Altera, EPM570GT100C5N Datasheet - Page 73
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EPM570GT100C5N
Manufacturer Part Number
EPM570GT100C5N
Description
IC MAX II CPLD 570 LE 100-TQFP
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM570GT100C5N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.4ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
570
Number Of Macrocells
440
Number Of I /o
76
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
1.8V
Memory Type
FLASH
Number Of Logic Elements/cells
570
Family Name
MAX II
# Macrocells
440
Frequency (max)
1.8797GHz
Propagation Delay Time
8.7ns
Number Of Logic Blocks/elements
57
# I/os (max)
76
Operating Supply Voltage (typ)
1.8V
In System Programmable
Yes
Operating Supply Voltage (min)
1.71V
Operating Supply Voltage (max)
1.89V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1405
EPM570GT100C5N
EPM570GT100C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM570GT100C5N
Manufacturer:
INTEL
Quantity:
1 235
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–21. UFM Block Internal Timing Microparameters (Part 2 of 3)
© August 2009 Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
Symbol
DDS
DDH
DP
PB
BP
PP M X
AE
EB
BE
EPM X
DCO
Data register data in
setup to data register
clock
Data register data in
hold from data
register clock
Program signal to
data clock hold time
Maximum delay
between program
rising edge to UFM
busy signal rising
edge
Minimum delay
allowed from UFM
busy signal going low
to program signal
going low
Maximum length of
busy pulse during a
program
Minimum erase signal
to address clock hold
time
Maximum delay
between the erase
rising edge to the
UFM busy signal
rising edge
Minimum delay
allowed from the UFM
busy signal going low
to erase signal going
low
Maximum length of
busy pulse during an
erase
Delay from data
register clock to data
register output
Parameter
Min
–3 Speed
20
20
—
20
—
—
20
—
—
0
0
Grade
Max
960
100
960
500
—
—
—
—
—
—
5
MAX II / MAX IIG
Min
–4 Speed
20
20
—
20
—
—
20
—
—
0
0
Grade
Max
960
100
960
500
—
—
—
—
—
—
5
Min
–5 Speed
20
20
—
20
—
—
20
—
—
0
0
Grade
Max
960
100
960
500
—
—
—
—
—
—
5
Min Max Min Max Min Max
–6 Speed
20
20
—
20
—
—
20
—
—
0
0
Grade
960
100
960
500
—
—
—
—
—
—
5
–7 Speed
20
20
—
20
—
—
20
—
—
MAX IIZ
0
0
Grade
960
100
960
500
—
—
—
—
—
—
5
MAX II Device Handbook
–8 Speed
20
20
—
20
—
—
20
—
—
0
0
Grade
960
100
960
500
—
—
—
—
—
—
5
Unit
ms
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
5–15