EPM570GT100C5N Altera, EPM570GT100C5N Datasheet - Page 33
![IC MAX II CPLD 570 LE 100-TQFP](/photos/6/70/67055/544-100-tqfp_sml.jpg)
EPM570GT100C5N
Manufacturer Part Number
EPM570GT100C5N
Description
IC MAX II CPLD 570 LE 100-TQFP
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM570GT100C5N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.4ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
570
Number Of Macrocells
440
Number Of I /o
76
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
1.8V
Memory Type
FLASH
Number Of Logic Elements/cells
570
Family Name
MAX II
# Macrocells
440
Frequency (max)
1.8797GHz
Propagation Delay Time
8.7ns
Number Of Logic Blocks/elements
57
# I/os (max)
76
Operating Supply Voltage (typ)
1.8V
In System Programmable
Yes
Operating Supply Voltage (min)
1.71V
Operating Supply Voltage (max)
1.89V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1405
EPM570GT100C5N
EPM570GT100C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM570GT100C5N
Manufacturer:
INTEL
Quantity:
1 235
Chapter 2: MAX II Architecture
I/O Structure
Figure 2–20. Row I/O Block Connection to the Interconnect
Note to
(1) Each of the seven IOEs in the row I/O block can have one data_out or fast_out output, one OE output, and one data_in input.
© October 2008 Altera Corporation
Figure
2–20:
LAB Local
Interconnect
Figure 2–20
R4 Interconnects
to Adjacent LAB
Interconnect
Direct Link
LAB
shows how a row I/O block connects to the logic array.
from Adjacent LAB
Interconnect
C4 Interconnects
Direct Link
data_in[6..0]
(Note 1)
LAB Column
clock [3..0]
I/O Block Local
Interconnect
data_out
7
7
fast_out
7
7
[6..0]
[6..0]
[6..0]
OE
Contains up to
Row I/O Block
I/O Block
Seven IOEs
Row
MAX II Device Handbook
2–25