EPM570GT100C5N Altera, EPM570GT100C5N Datasheet - Page 34

• Manufacturer Part Number: EPM570GT100C5N
• Description: IC MAX II CPLD 570 LE 100-TQFP
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM570GT100C5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.4ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 570
• Number Of Macrocells: 440
• Number Of I /o: 76
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 1.8V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 570
• Family Name: MAX II
• # Macrocells: 440
• Frequency (max): 1.8797GHz
• Propagation Delay Time: 8.7ns
• Number Of Logic Blocks/elements: 57
• # I/os (max): 76
• Operating Supply Voltage (typ): 1.8V
• In System Programmable: Yes
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1405; EPM570GT100C5N

2–26
Figure 2–21. Column I/O Block Connection to the Interconnect
Note to
(1) Each of the four IOEs in the column I/O block can have one data_out or fast_out output, one OE output, and one data_in input.
I/O Standards and Banks
MAX II Device Handbook
Figure
Local Interconnect
2–21:
I/O Block
LAB Local
Interconnect
Figure 2–21
MAX II device IOEs support the following I/O standards:
■
■
■
■
■
R4 Interconnects
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
data_out
C4 Interconnects
[3..0]
shows how a column I/O block connects to the logic array.
LAB
4
[3..0]
OE
4
Column I/O Block
Interconnect
LAB Local
Interconnect
fast_out
Fast I/O
(Note 1)
[3..0]
Path
LAB
4
LAB Column
Clock [3..0]
4
data_in
[3..0]
C4 Interconnects
© October 2008 Altera Corporation
Column I/O
Block Contains
Up To 4 IOEs
LAB Local
Interconnect
Chapter 2: MAX II Architecture
LAB
I/O Structure