C8051F336-GMR Silicon Laboratories Inc, C8051F336-GMR Datasheet - Page 95
![Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free](/photos/16/2/160285/qfn-20_sml.jpg)
C8051F336-GMR
Manufacturer Part Number
C8051F336-GMR
Description
Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F336-GM.pdf
(226 pages)
Specifications of C8051F336-GMR
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
768 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-20
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F336DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
10 bit
Package
20QFN
Device Core
8051
Family Name
C8051F336
Maximum Speed
25 MHz
Ram Size
768 Byte
Operating Temperature
-40 to 85 °C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F336-GMR
Manufacturer:
SILICON
Quantity:
100
Part Number:
C8051F336-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
16.4. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of V
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
The following guidelines are recommended for any system which contains routines which write or erase
Flash from code.
16.4.1. V
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
2. Make certain that the minimum V
3. Enable the on-chip V
4. As an added precaution, explicitly enable the V
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas to check
16.4.2. PSWE Maintenance
7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a '1'. There should be
8. Minimize the number of variable accesses while PSWE is set to a '1'. Handle pointer address updates
9. Disable interrupts prior to setting PSWE to a '1' and leave them disabled until after PSWE has been
10.Make certain that the Flash write and erase pointer variables are not located in XRAM. See your
devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings
table are not exceeded.
this rise time specification, then add an external V
holds the device in reset until V
possible. This should be the first set of instructions executed after the Reset Vector. For 'C'-based
systems, this will involve modifying the startup code added by the 'C' compiler. See your compiler
documentation for more details. Make certain that there are no delays in software between enabling the
V
found in “AN201: Writing to Flash from Firmware", available from the Silicon Laboratories web site.
source inside the functions that write and erase Flash memory. The V
should be placed just after the instruction to set PSWE to a '1', but before the Flash write or erase
operation instruction.
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC =
0x02" is correct. "RSTSRC |= 0x02" is incorrect.
are initialization code which enables other reset sources, such as the Missing Clock Detector or
Comparator, for example, and instructions which force a Software Reset. A global search on "RSTSRC"
can quickly verify this.
exactly one routine in code that sets PSWE to a '1' to write Flash bytes and one routine in code that
sets PSWE and PSEE both to a '1' to erase Flash pages.
and loop variable maintenance outside the "PSWE = 1;... PSWE = 0;" area. Code examples showing
this can be found in AN201, "Writing to Flash from Firmware", available from the Silicon Laboratories
web site.
reset to '0'. Any interrupts posted during the Flash write or erase operation will be serviced in priority
order after the Flash operation has been completed and interrupts have been re-enabled by software.
compiler documentation for instructions regarding how to explicitly locate variables in different memory
DD
monitor and enabling the V
DD
Maintenance and the V
DD
, system clock frequency, or temperature. This accidental execution of Flash modi-
DD
monitor and enable the V
DD
DD
DD
DD
reaches 2.7 V and re-asserts RST if V
monitor as a reset source. Code examples showing this can be
rise time specification of 1 ms is met. If the system cannot meet
monitor
Rev.1.0
DD
DD
DD
monitor and enable the V
monitor as a reset source as early in code as
brownout circuit to the RST pin of the device that
C8051F336/7/8/9
DD
monitor enable instructions
DD
DD
drops below 2.7 V.
monitor as a reset
95