C8051F336-GMR Silicon Laboratories Inc, C8051F336-GMR Datasheet - Page 78

• Manufacturer Part Number: C8051F336-GMR
• Description: Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F336-GMR

• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-20
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F336DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 10 bit
• Package: 20QFN
• Device Core: 8051
• Family Name: C8051F336
• Maximum Speed: 25 MHz
• Ram Size: 768 Byte
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

C8051F336/7/8/9
14. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051F336/7/8/9's resources and peripher-
als. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as
implementing additional SFRs used to configure and access the sub-systems unique to the
C8051F336/7/8/9. This allows the addition of new functionality while retaining compatibility with the MCS-
51™ instruction set. Table 14.1 lists the SFRs implemented in the C8051F336/7/8/9 device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 14.2, for a detailed description of each register.
78
Note: SFR Addresses ending in 0x0 or 0x8 are bit-addressable locations and can be used with bitwise instructions.
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2
E0
D8 PCA0CN
D0
C8 TMR2CN
C0 SMB0CN
B8
B0
A8
A0
F8
F0
98
90
88
80
SPI0CN
SCON0
TCON
PSW
ACC
0(8)
P2
P1
P0
IP
IE
B
Table 14.1. Special Function Register (SFR) Memory Map
OSCXCN
SPI0CFG
PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2
TMR3CN
REF0CN
SMB0CF
CLKSEL
P0MDIN
IDA0CN
SBUF0
PCA0L
TMOD
XBR0
1(9)
SP
SMB0DAT ADC0GTL ADC0GTH ADC0LTL
TMR2RLL TMR2RLH
TMR3RLL TMR3RLH
SPI0CKR
OSCICN
P1MDIN
EMI0CN
AMX0N
PCA0H
XBR1
DPL
2(A)
TL0
PCA0CPL0 PCA0CPH0
OSCLCN
SPI0DAT
CPT0CN
P2MDIN
OSCICL
AMX0P
DPH
3(B)
TL1
Rev.1.0
P0MDOUT P1MDOUT P2MDOUT
ADC0CF
P0SKIP
IT01CF
TMR2L
TMR3L
TH0
4(C)
CPT0MD
P1SKIP
TMR2H
TMR3H
P0MAT
P1MAT
ADC0L
5(D)
TH1
ADC0LTH
P0MASK
P1MASK
CKCON
P2SKIP
ADC0H
FLSCL
IDA0L
EIP1
EIE1
6(E)
PCA0PWM
SMB0ADM
SMB0ADR
VDM0CN
RSTSRC
CPT0MX
PSCTL
FLKEY
IDA0H
PCON
7(F)