C8051F336-GMR Silicon Laboratories Inc, C8051F336-GMR Datasheet - Page 107

• Manufacturer Part Number: C8051F336-GMR
• Description: Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F336-GMR

• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-20
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F336DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 10 bit
• Package: 20QFN
• Device Core: 8051
• Family Name: C8051F336
• Maximum Speed: 25 MHz
• Ram Size: 768 Byte
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

C8051F336/7/8/9
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This pro-
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi-
nitely, waiting for an external stimulus to wake up the system. Refer to
Section “17.6. PCA Watchdog
Timer Reset” on page 104
for more information on the use and configuration of the WDT.
18.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter Stop mode as soon as the
instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital
peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop
mode can only be terminated by an internal or external reset. On reset, the device performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 µs.
18.3. Suspend Mode
Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the CPU and the high-frequency inter-
nal oscillator, and go into Suspend mode as soon as the instruction that sets the bit completes execution.
All internal registers and memory maintain their original data. Most digital peripherals are not active in Sus-
pend mode. The exception to this is the Port Match feature and Timer 3, when it is run from an external
oscillator source or the internal low-frequency oscillator.
Suspend mode can be terminated by four types of events, a port match (described in
Section “20.5. Port
Match” on page
129), a Timer 3 overflow (described in
Section “24.3. Timer 3” on page
196), a Com-
parator low output (if enabled), or a device reset event. Note that in order to run Timer 3 in Suspend mode,
the timer must be configured to clock from either the external clock source or the internal low-frequency
oscillator source. When Suspend mode is terminated, the device will continue execution on the instruction
following the one that set the SUSPEND bit. If the wake event (port match or Timer 3 overflow) was config-
ured to generate an interrupt, the interrupt will be serviced upon waking the device. If Suspend mode is ter-
minated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins
program execution at address 0x0000.
Rev.1.0
107