M25PX16-VMW6G Micron Technology Inc, M25PX16-VMW6G Datasheet - Page 42
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M25PX16-VMW6G
Manufacturer Part Number
M25PX16-VMW6G
Description
Manufacturer
Micron Technology Inc
Datasheet
1.M25PX16-VMW6G.pdf
(65 pages)
Specifications of M25PX16-VMW6G
Cell Type
NOR
Density
16Mb
Access Time (max)
8ns
Interface Type
Serial (SPI)
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
2.5/3.3V
Operating Temp Range
-40C to 85C
Package Type
SO W
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
2M
Supply Current
12mA
Mounting
Surface Mount
Pin Count
8
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M25PX16-VMW6G
Manufacturer:
ST
Quantity:
20 000
6.18
42/65
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is t
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits
are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 25. Bulk Erase (BE) instruction sequence
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the Deep Power-down mode). It can also be used as a software
protection mechanism, while the device is not in active use, as in this mode, the device
ignores all Write, Program and Erase instructions.
Driving Chip Select (S) High deselects the device, and puts the device in the Standby Power
mode (if there is no internal cycle currently in progress). But this mode is not the Deep
Power-down mode. The Deep Power-down mode can only be entered by executing the
Deep Power-down (DP) instruction, subsequently reducing the standby current (from I
I
To take the device out of Deep Power-down mode, the Release from Deep Power-down
(RDP) instruction must be issued. No other instruction must be issued while the device is in
Deep Power-down mode.
The Deep Power-down mode automatically stops at power-down, and the device always
powers up in the Standby Power mode.
The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for
the entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as
CC2
, as specified in
S
C
DQ0
Table
17).
Figure
0
1
2
26.
Instruction
3
4
5
6
7
BE
AI13743
) is initiated. While the
CC1
to