M25PX16-VMW6G Micron Technology Inc, M25PX16-VMW6G Datasheet - Page 40

• Manufacturer Part Number: M25PX16-VMW6G
• Manufacturer: Micron Technology Inc

Specifications of M25PX16-VMW6G

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SO W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

6.15
40/65
Table 10.
1. Values of (b1, b0) after power-up are defined in
Subsector Erase (SSE)
The Subsector Erase (SSE) instruction sets to 1 (FFh) all bits inside the chosen subsector.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been
executed. After the Write Enable (WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
The Subsector Erase (SSE) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code, and three address bytes on Serial Data input (DQ0). Any address
inside the Subsector (see
instruction. Chip Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Subsector Erase (SSE) instruction is not executed. As soon as
Chip Select (S) is driven High, the self-timed Subsector Erase cycle (whose duration is t
is initiated. While the Subsector Erase cycle is in progress, the Status Register may be read
to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Subsector Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Subsector Erase (SSE) instruction issued to a sector that is hardware or software
protected, is not executed.
Any Subsector Erase (SSE) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 23. Subsector Erase (SSE) instruction sequence
1. Address bits A23 to A22 are Don’t care.
All sectors
Sector
S
C
DQ0
Lock Register in
0
b7-b2
Table
Bit
b1
b0
1
2
(1)
Instruction
4) is a valid address for the Subsector Erase (SSE)
3
Sector Lock Down bit value (refer to
Sector Write Lock bit value (refer to
4
Figure
5
Section 7: Power-up and
6
7
23.
MSB
23 22
8
9
24 Bit Address
Value
‘0’
2
29 30 31
power-down.
1
Table
Table
0
9)
9)
AI13741
SSE
)