M25PX16-VMW6G Micron Technology Inc, M25PX16-VMW6G Datasheet - Page 26

• Manufacturer Part Number: M25PX16-VMW6G
• Manufacturer: Micron Technology Inc

Specifications of M25PX16-VMW6G

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SO W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

6.4.1
6.4.2
6.4.3
6.4.4
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Table 7.
The status and control bits of the Status Register are as follows:
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to
0 no such cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as defined in
protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect
(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,
BP1, BP0) bits are 0.
TB bit
The Top/Bottom (TB) bit is non-volatile. It can be set and reset with the Write Status Register
(WRSR) instruction provided that the Write Enable (WREN) instruction has been issued.
The Top/Bottom (TB) bit is used in conjunction with the Block Protect (BP0, BP1, BP2) bits
to determine if the protected area defined by the Block Protect bits starts from the top or the
bottom of the memory array:
The TB bit cannot be written when the SRWD bit is set to ‘1’ and the W pin is driven Low.
Status Register Write Protect
SRWD
When TB is reset to ‘0’ (default value), the area protected by the Block Protect bits
starts from the top of the memory array (see
When TB is set to ‘1’, the area protected by the Block Protect bits starts from the
bottom of the memory array (see
b7
Status Register format
0
Top/Bottom bit
TB
Table 3: Protected area
BP2
Block Protect bits
Table 3: Protected area
BP1
Write Enable Latch bit
BP0
sizes)
Table
WEL
Write In Progress bit
3) becomes
sizes)
WIP
b0