IDT49C466PQF IDT, Integrated Device Technology Inc, IDT49C466PQF Datasheet - Page 5

• Manufacturer Part Number: IDT49C466PQF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT49C466PQF

• Lead Free Status / Rohs Status: Not Compliant

PIN DESCRIPTION (cont.)
IDT49C466, IDT49C466A
64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
RBSEL
RBEN
RBREN
CBSEL
MEN
Clock Inputs
MCLK
SCLK
SYNCLK
Status Outputs
WBEF
WBFF
RBEF
RBHF
RBFF
ERR
MERR
PERR
Power Supply
V
GND
CC
Pin Name
I/O
O
O
O
O
O
O
O
O
P
P
I
I
I
I
I
I
I
I
Read FIFO Select: when HIGH, read FIFO is selected (data goes through read FIFO, not MD output latch). When LOW,
the MD output latch is selected.
Read FIFO Enable: when LOW, allows data to be written into the read FIFO on the LOW-to-HIGH transition of the memory
clock.
Read FIFO Enable: when LOW, allows data to be read from the read FIFO on the LOW-to-HIGH transition of SCLK.
Checkbit Syndrome Output Enable: controls the CBSYN output buffer.When HIGH, the buffer is enabled. When CBSEL
is LOW, MOE controls the buffer.
Mode Enable Input: when LOW, SD
This pin must be held LOW for the entire SCLK HIGH period, as shown in Figure 4.
Memory Clock: on the LOW-to-HIGH transition of MCLK, memory data is written to the read FIFO when RBEN is LOW.
Data is read from the write FIFO when WBREN is LOW, on the LOW-to-HIGH transition of MCLK.
System Clock: on the LOW-to-HIGH transition of the SCLK, data is read from the read FIFO when RBREN is LOW.
Data on the system data bus is written into the write FIFO when WBEN is LOW on the LOW-to-HIGH transition of SCLK.
Clocks data into mode register when MEN is LOW.
Syndrome Clock: used to load diagnostic registers. When an error occurs, Error Counter is incremented on the rising
SYNCLK edge (up to 15 errors). On the first error after a diagnostic reset, SYNCLK rising edge clocks data into Check
Bit, Syndrome, Error Type and Error Data registers. One of the syndrome registers has new data clocked in on every
SYNCLK rising edge.
Write FIFO Empty Flag: when LOW, indicates that the write FIFO is empty. After a reset, the WBEF goes LOW.
Write FIFO Full Flag: when LOW, indicates that the write FIFO is full. After a reset, WBFF goes HIGH.
Read FIFO Empty Flag: when LOW, indicates that the read FIFO is empty. After a reset, the RBEF goes LOW.
Read FIFO Half-full Flag: when LOW, indicates that there are eight or more data words (in the 16-deep configuration) or
four or more data words (in the dual 8-deep configuration) in the read FIFO. The flag will return HIGH when less than eight
(or four) data words are in the FIFO.
Read FIFO Full Flag: when LOW, indicates that the read FIFO is full. After a reset, RBFF goes HIGH.
Error Flag: when ERR is LOW, a data error is indicated. The ERR is not latched internally.
Multiple Error Flag: when MERR is LOW, a multiple data error is indicated. The MERR is not latched internally.
Parity Error Flag: when LOW, indicates a parity error on the system data bus input.
Power Supply Voltage.
Ground.
0-15
5
is loaded into the EDC mode register on the LOW-to-HIGH transition of the SCLK.
Description
COMMERCIAL TEMPERATURE RANGE