IDT72V283L7-5PF9 IDT, Integrated Device Technology Inc, IDT72V283L7-5PF9 Datasheet - Page 42
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IDT72V283L7-5PF9
Manufacturer Part Number
IDT72V283L7-5PF9
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT72V283L7-5PF9.pdf
(45 pages)
Specifications of IDT72V283L7-5PF9
Configuration
Dual
Density
576Kb
Access Time (max)
5ns
Word Size
9/18Bit
Organization
32Kx18/64Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
133.3MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
30@9BIT/35@18BITmA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
80
Lead Free Status / Rohs Status
Not Compliant
TEST ACCESS PORT (TAP)
internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST)
and one output port (TDO).
JTAG INTERFACE
support the JTAG boundary scan interface. The IDT72V223/72V233/72V243/
72V253/72V263/72V273/72V283/72V293 incorporates the necessary tap
controller and modified pad cells to implement the JTAG facility.
program files for these devices.
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
The Tap interface is a general-purpose port that provides access to the
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
Note that IDT provides appropriate Boundary Scan Description Language
TDO
TDI
TMS
TCLK
TRST
T
A
P
Cont-
roller
TAP
clkDR, ShiftDR
clklR, ShiftlR
UpdatelR
UpdateDR
Figure 32. Boundary Scan Architecture
Instruction Register
Control Signals
42
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
THE TAP CONTROLLER
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and update of data.
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
TM
The Standard JTAG interface consists of four basic elements:
•
•
•
•
The following sections provide a brief description of each element. For a
The Figure below shows the standard Boundary-Scan Architecture
The Tap controller is a synchronous finite state machine that responds to
NARROW BUS FIFO
Test Access Port (TAP)
TAP controller
Instruction Register (IR)
Data Register Port (DR)
Instruction Decode
Mux
4666 drw35
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009