MT45W256KW16PEGA-70 WT Micron Technology Inc, MT45W256KW16PEGA-70 WT Datasheet - Page 9

• Manufacturer Part Number: MT45W256KW16PEGA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W256KW16PEGA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Functional Description
Power-Up Initialization
Figure 4:
Bus Operating Modes
Asynchronous Mode
PDF: 09005aef8329b746 / Source: 09005aef82f264aa
8mb_4mb_asyncpage_cr1_0_p22z__2.fm - Rev. B 4/08 EN
Power-Up Initialization Timing
In general, the MT45W256KW16PEGA devices are high-density alternatives to SRAM
and PSRAM products, which are popular in low-power, portable applications.
MT45W256KW16PEGA devices contain a 4,194,304-bit DRAM core organized as 262,144
addresses by 16 bits. These devices include the industry-standard, asynchronous
memory interface found on other low-power SRAM or PSRAM offerings.
Page mode accesses are also included as a bandwidth-enhancing extension to the asyn-
chronous read protocol.
CellularRAM products include an on-chip voltage sensor that is used to launch the
power-up initialization process. Initialization will load the CR with its default setting.
V
1.7V, the device will require 150µs to complete its self-initialization process (see
Figure 4). During the initialization period, CE# should remain HIGH. When initialization
is complete, the device is ready for normal operation.
The MT45W256KW16PEGA CellularRAM product incorporates the industry-standard,
asynchronous interface. This bus interface supports asynchronous READ and WRITE
operations as well as page mode READ operation for enhanced bandwidth. The
supported interface is defined by the value loaded into the CR.
CellularRAM products power up in the asynchronous operating mode. This mode uses
the industry-standard SRAM control interface (CE#, OE#, WE#, and LB#/UB#). READ
operations (Figure 5 on page 10) are initiated by bringing CE#, OE#, and LB#/UB# LOW
while keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified
access time has elapsed. WRITE operations (Figure 6 on page 10) occur when CE#, WE#,
and LB#/UB# are driven LOW. During WRITE operations, the level of OE# is a “Don’t
Care”; WE# will override OE#. The data to be written will be latched on the rising edge of
CE#, WE#, or LB#/UB#, whichever occurs first. WE# LOW time must be limited to
Vcc, VccQ = 1.7V
CC
and V
CC
Q must be applied simultaneously, and when they reach a stable level above
4Mb: 256K x16 Async/Page CellularRAM 1.0 Memory
t PU
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
normal operation
Device ready for
Vcc (MIN)
Functional Description
©2008 Micron Technology, Inc. All rights reserved.
t
CEM.