MT45W256KW16PEGA-70 WT Micron Technology Inc, MT45W256KW16PEGA-70 WT Datasheet
MT45W256KW16PEGA-70 WT
Specifications of MT45W256KW16PEGA-70 WT
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MT45W256KW16PEGA-70 WT Summary of contents
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... DQ3 E VccQ DQ12 NC A16 DQ4 F DQ14 DQ13 A14 A15 DQ5 G DQ15 NC A12 A13 WE# H DNU A8 A9 A10 A11 Top view (Ball down) Part Number Example: MT45W256KW16PEGA-70WT ©2008 Micron Technology, Inc. All rights reserved. Features 6 ZZ# DQ0 DQ2 Vcc Vss DQ6 DQ7 NC ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 48-Ball VFBGA Ball Assignments ...
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List of Tables Table 1: VFBGA Ball Descriptions ...
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General Description Micron power, portable applications. The MT45W256KW16PE is a 4Mb DRAM core device orga- nized as 256K x 16 bits. These devices include the industry-standard, asynchronous memory interface found on other low-power SRAM or pseudo-SRAM (PSRAM) offerings. For seamless ...
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Ball Descriptions Table 1: VFBGA Ball Descriptions VFBGA Ball Assignment Symbol D3, E4, F4, F3, G4, A[17:0] G3, H5, H4, H3, H2, D4, C4, C3, B4, B3, A5, A4 CE# A1 LB# A2 OE# B2 UB# G5 WE# ...
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Bus Operations Table 2: Bus Operations Mode Standby Read Write No operation PAR Partial-array refresh Deep power-down DPD Load configuration register Notes: 1. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# alone is in ...
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Part Numbering Information Micron CellularRAM devices are available in several configurations and densities (see Figure 3). Figure 3: Part Number Chart Micron Technology Product Family 45 = PSRAM/CellularRAM memory Operating Core Voltage W = 1.7–1.95V Address Locations K = Kilobits ...
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... Functional Description In general, the MT45W256KW16PEGA devices are high-density alternatives to SRAM and PSRAM products, which are popular in low-power, portable applications. MT45W256KW16PEGA devices contain a 4,194,304-bit DRAM core organized as 262,144 addresses by 16 bits. These devices include the industry-standard, asynchronous memory interface found on other low-power SRAM or PSRAM offerings. ...
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Figure 5: READ Operation CE# OE# WE# Address Data LB#/UB# Figure 6: WRITE Operation CE# OE# WE# Address Data LB#/UB# PDF: 09005aef8329b746 / Source: 09005aef82f264aa 8mb_4mb_asyncpage_cr1_0_p22z__2.fm - Rev. B 4/08 EN 4Mb: 256K x16 Async/Page CellularRAM 1.0 Memory Valid address ...
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Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the low- order address. ...
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Low-Power Operation Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM REFRESH operation on the full array. Standby operation occurs when CE# and ZZ# are HIGH. The device will enter ...
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Figure 8: Software Access PAR Functionality No Deep Power-Down Operation Deep power-down (DPD) operation disables all refresh-related activity. This mode is used when the system does not require the storage provided by the CellularRAM device. Any stored data will become ...
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Configuration Register Operation The configuration register (CR) defines how the CellularRAM device performs its trans- parent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the CR. This ...
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Software Access to the Configuration Register The contents of the CR either can be read or modified using a software sequence. The nature of this access mechanism may eliminate the need for the ZZ# ball. If the software mechanism is ...
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Figure 12: Read Configuration Register Address CE# OE# WE# LB#/UB# Data Notes possible that the data stored at the highest memory location will be altered if the data at the falling edge of WE# is not 0000h. ...
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Electrical Characteristics Stresses greater than those listed in Table 3 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the ...
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Table 4: Electrical Characteristics and Operating Conditions Wireless temperature Description Supply voltage I/O supply voltage Input high voltage Input low voltage Output high voltage I OH Output low voltage I OL Input leakage current V IN Output leakage current OE# ...
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Maximum and Typical Standby Currents The maximum and typical standby currents for the MT45W256KW16PE device are shown in Figure 13. Figure 13: Typical Refresh Current vs. Temperature –45 –35 –25 –15 –5 ...
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Table 5: Deep Power-Down Specifications and Conditions Description Deep power-down Table 6: Capacitance Specifications and Conditions Description Input capacitance Input/output capacitance (DQ) Notes: 1. These parameters are verified in device characterization and are not 100% tested. Figure 14: AC Input/Output ...
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Table 7: READ Cycle Timing Requirements Parameter Address access time Page access time LB#/UB# access time LB#/UB# disable to High-Z output LB#/UB# enable to Low-Z output Maximum CE# pulse width Chip select access time Chip disable to High-Z output Chip ...
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Table 8: WRITE Cycle Timing Requirements Parameter Address setup time Address valid to end of write Byte select to end of write CE# HIGH time during write Chip enable to end of write Data hold from write time Data write ...
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Timing Diagrams Table 11: Initialization Timing Parameters Parameter Initialization period (required before normal operations) Figure 16: Power-Up Initialization Period Vcc, VccQ = 1.7V Figure 17: Load Configuration Register Address CE# LB#/UB# WE# OE# ZZ# Figure 18: Deep Power-Down Entry and ...
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Figure 19: Single READ Operation (WE Address CE# LB#/UB# OE# Data out Figure 20: Page Mode READ Operation (WE Address A[17:4] Address A[3:0] CE# LB#/UB# OE# Data out PDF: 09005aef8329b746 / Source: 09005aef82f264aa 8mb_4mb_asyncpage_cr1_0_p22z__2.fm - Rev. ...
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Figure 21: WRITE Cycle (WE# Control) Address CE# LB#/UB# WE# OE# Data in Data out Figure 22: WRITE Cycle (CE# Control) Address CE# LB#/UB# WE# OE# Data in Data out PDF: 09005aef8329b746 / Source: 09005aef82f264aa 8mb_4mb_asyncpage_cr1_0_p22z__2.fm - Rev. B 4/08 ...
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Figure 23: WRITE Cycle (LB#/UB# Control) Address CE# LB#/UB# WE# OE# Data in Data out PDF: 09005aef8329b746 / Source: 09005aef82f264aa 8mb_4mb_asyncpage_cr1_0_p22z__2.fm - Rev. B 4/08 EN 4Mb: 256K x16 Async/Page CellularRAM 1.0 Memory t WC Valid address ...
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Package Dimensions Figure 24: 48-Ball VFBGA 0.70 ±0.05 Seating plane A 0.10 A 48X Ø0.37 Dimensions apply to solder balls post-reflow. Pre-reflow ball diameter is 0. 0.30 SMD ball pad. Ball A6 5.25 2.625 1.875 6.00 ±0.10 Notes: ...
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Revision History Rev. B, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...