MT47H32M16HR-25E IT:F TR Micron Technology Inc, MT47H32M16HR-25E IT:F TR Datasheet - Page 7
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MT47H32M16HR-25E IT:F TR
Manufacturer Part Number
MT47H32M16HR-25E IT:F TR
Description
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet
1.MT47H32M16HR-25E_ITF_TR.pdf
(131 pages)
Specifications of MT47H32M16HR-25E IT:F TR
Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
400ps
Maximum Clock Rate
800MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
295mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant
List of Tables
Table 1: Key Timing Parameters ...................................................................................................................... 2
Table 2: Addressing ......................................................................................................................................... 2
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions .......................................................................... 15
Table 4: Input Capacitance ............................................................................................................................ 19
Table 5: Absolute Maximum DC Ratings ........................................................................................................ 20
Table 6: Temperature Limits .......................................................................................................................... 21
Table 7: Thermal Impedance ......................................................................................................................... 21
Table 8: General I
Table 9: I
Table 10: DDR2 I
Table 11: DDR2 I
Table 12: AC Operating Specifications and Conditions .................................................................................... 30
Table 13: Recommended DC Operating Conditions (SSTL_18) ........................................................................ 41
Table 14: ODT DC Electrical Characteristics ................................................................................................... 42
Table 15: Input DC Logic Levels ..................................................................................................................... 43
Table 16: Input AC Logic Levels ..................................................................................................................... 43
Table 17: Differential Input Logic Levels ........................................................................................................ 44
Table 18: Differential AC Output Parameters .................................................................................................. 46
Table 19: Output DC Current Drive ................................................................................................................ 46
Table 20: Output Characteristics .................................................................................................................... 47
Table 21: Full Strength Pull-Down Current (mA) ............................................................................................ 48
Table 22: Full Strength Pull-Up Current (mA) ................................................................................................. 49
Table 23: Reduced Strength Pull-Down Current (mA) ..................................................................................... 50
Table 24: Reduced Strength Pull-Up Current (mA) .......................................................................................... 51
Table 25: Input Clamp Characteristics ........................................................................................................... 52
Table 26: Address and Control Balls ............................................................................................................... 53
Table 27: Clock, Data, Strobe, and Mask Balls ................................................................................................. 53
Table 28: AC Input Test Conditions ................................................................................................................ 54
Table 29: DDR2-400/533 Setup and Hold Time Derating Values (
Table 30: DDR2-667/800/1066 Setup and Hold Time Derating Values (
Table 31: DDR2-400/533
Table 32: DDR2-667/800/1066
Table 33: Single-Ended DQS Slew Rate Derating Values Using
Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V
Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V
Table 36: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V
Table 37: Truth Table – DDR2 Commands ..................................................................................................... 68
Table 38: Truth Table – Current State Bank n – Command to Bank n ............................................................... 69
Table 39: Truth Table – Current State Bank n – Command to Bank m .............................................................. 71
Table 40: Minimum Delay with Auto Precharge Enabled ................................................................................. 72
Table 41: Burst Definition .............................................................................................................................. 76
Table 42: READ Using Concurrent Auto Precharge ......................................................................................... 96
Table 43: WRITE Using Concurrent Auto Precharge ....................................................................................... 102
Table 44: Truth Table – CKE ......................................................................................................................... 117
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. Q 10/10 EN
DD7
Timing Patterns (4-Bank Interleave READ Operation) ................................................................. 23
DD
DD
DD
Specifications and Conditions (Die Revision F) ................................................................ 24
Specifications and Conditions (Die Revision G) ................................................................ 27
Parameters .................................................................................................................... 23
t
DS,
t
DH Derating Values with Differential Strobe ..................................................... 60
t
DS,
t
DH Derating Values with Differential Strobe ............................................ 61
7
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DS
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
IS and
b
and
REF
REF
REF
512Mb: x4, x8, x16 DDR2 SDRAM
t
) at DDR2-667 ..................................... 62
) at DDR2-533 ..................................... 63
) at DDR2-400 ..................................... 63
IS and
t
t
DH
IH) ................................................... 56
b
.................................................. 62
t
IH) .......................................... 57
© 2004 Micron Technology, Inc. All rights reserved.
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