MT48LC4M16A2P-75 L:GTR Micron Technology Inc, MT48LC4M16A2P-75 L:GTR Datasheet - Page 67
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MT48LC4M16A2P-75 L:GTR
Manufacturer Part Number
MT48LC4M16A2P-75 L:GTR
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC4M16A2P-75_LGTR.pdf
(72 pages)
Specifications of MT48LC4M16A2P-75 L:GTR
Organization
4Mx16
Density
64Mb
Address Bus
14b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
140mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
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Figure 50:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
DQML, DQMH
COMMAND
A0–A9, A11
BA0, BA1
DQM /
CKE
CLK
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
T0
ROW
ROW
BANK
Single WRITE – With Auto Precharge
t CMH
t CKH
t AH
t AH
t AH
t RCD
t RAS
t RC
Notes:
t CK
T1
NOP 3
1. For this example, BL = 1.
2. x16: A8, A9 and A11 = “Don’t Care”
3. WRITE command not allowed or
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
t CL
NOP 3
T2
t CH
T3
NOP 3
ENABLE AUTO PRECHARGE
t CMS
COLUMN m 2
t DS
BANK
WRITE
T4
D
IN
t CMH
t DH
m
67
t WR
t
RAS would be violated.
T5
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T6
NOP
t RP
64Mb: x4, x8, x16 SDRAM
T7
NOP
©2000 Micron Technology, Inc. All rights reserved.
Timing Diagrams
ACTIVE
ROW
ROW
BANK
T8
T9
NOP
DON’T CARE
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