MT48LC4M16A2P-75 L:GTR Micron Technology Inc, MT48LC4M16A2P-75 L:GTR Datasheet - Page 36
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MT48LC4M16A2P-75 L:GTR
Manufacturer Part Number
MT48LC4M16A2P-75 L:GTR
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC4M16A2P-75_LGTR.pdf
(72 pages)
Specifications of MT48LC4M16A2P-75 L:GTR
Organization
4Mx16
Density
64Mb
Address Bus
14b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
140mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Figure 27:
Figure 28:
Concurrent Auto Precharge
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
Clock Suspend During WRITE Burst
Clock Suspend During READ Burst
Note:
COMMAND
COMMAND
An access command (READ or WRITE) to another bank while an access command with
auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM
supports concurrent auto precharge. Micron SDRAMs support concurrent auto
precharge. Four cases where concurrent auto precharge occurs are defined below.
INTERNAL
INTERNAL
ADDRESS
ADDRESS
CLOCK
CLOCK
For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
CLK
CKE
CLK
CKE
D
DQ
IN
NOP
T0
BANK,
COL n
T0
READ
WRITE
BANK,
COL n
T1
T1
D
NOP
n
IN
TRANSITIONING DATA
T2
T2
NOP
36
D
OUT
n
TRANSITIONING DATA
T3
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n + 1
D
OUT
NOP
n + 1
T4
T4
D
NOP
IN
DON’T CARE
T5
T5
NOP
n + 2
D
NOP
IN
n + 2
D
OUT
64Mb: x4, x8, x16 SDRAM
DON’T CARE
T6
NOP
D
n + 3
OUT
©2000 Micron Technology, Inc. All rights reserved.
Commands