MT48LC4M16A2P-75 L:GTR Micron Technology Inc, MT48LC4M16A2P-75 L:GTR Datasheet - Page 53
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT48LC4M16A2P-75 L:GTR
Manufacturer Part Number
MT48LC4M16A2P-75 L:GTR
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC4M16A2P-75_LGTR.pdf
(72 pages)
Specifications of MT48LC4M16A2P-75 L:GTR
Organization
4Mx16
Density
64Mb
Address Bus
14b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
140mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Figure 36:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
DQML, DQMH
Power-Down Mode
COMMAND
A0–A9, A11
Precharge all
DQM /
BA0, BA1
active banks
Notes:
CLK
CKE
A10
DQ
High-Z
t CKS
t CMS
t AS
SINGLE BANK
PRECHARGE
ALL BANKS
BANK(S)
1. Violating refresh requirements during power-down may result in a loss of data.
T0
t CMH
t CKH
t AH
Two clock cycles
All banks idle, enter
power-down mode
t CK
T1
NOP
t CKS
t CL
T2
NOP
Input buffers gated off while in
power-down mode
t CH
53
Exit power-down mode
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
)
(
)
)
)
)
)
(
)
(
)
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
)
(
)
)
)
)
)
(
)
(
)
)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t CKS
Tn + 1
NOP
All banks idle
64Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
Tn + 2
ACTIVE
ROW
ROW
BANK
DON’T CARE
Timing Diagrams