MT48H32M16LFCJ-75 Micron Technology Inc, MT48H32M16LFCJ-75 Datasheet - Page 41

• Manufacturer Part Number: MT48H32M16LFCJ-75
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48H32M16LFCJ-75

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 9/6ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Truth Tables
Table 6:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
CKE
H
H
L
L
n-1
CKE
H
H
Truth Table – CKE
Notes: 1–4
L
L
n
Notes:
Deep power-down
Deep power-down
Reading or writing
Current State
Clock suspend
Clock suspend
All banks idle
All banks idle
All banks idle
Power-Down
Power-Down
Self refresh
Self refresh
1. CKE
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. Deep power-down is power savings feature of this Mobile SDRAM device. This command is
6. Exiting power-down at clock edge n will put the device in the all banks idle state in time for
7. Exiting self refresh at clock edge n will put the device in the all banks idle state once
8. After exiting clock suspend at clock edge n, the device will resume operation and recognize
clock edge.
of COMMAND
BURST TERMINATE when CKE is HIGH and deep power-down when CKE is LOW.
clock edge n + 1 (provided that
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring
during the
t
the next command at clock edge n + 1.
XSR period.
n
is the logic state of CKE at clock edge n; CKE
t
n
XSR period. A minimum of two NOP commands must be provided during the
is the command registered at clock edge n, and ACTION
n
.
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
Table 8 on page 44
BURST TERMINATE
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
AUTO REFRESH
Command
VALID
41
X
X
X
X
X
X
t
CKS is met).
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n-1
Maintain deep power-down
Deep power-down entry
was the state of CKE at the previous
Maintain clock suspend
Exit deep power-down
Maintain power-down
Maintain self refresh
Clock suspend entry
Power-Down entry
Exit clock suspend
Exit power-down
Self refresh entry
Exit self refresh
Action
©2005 Micron Technology, Inc. All rights reserved.
n
n
is a result
Truth Tables
Notes
t
XSR is
5
6
5
7
8
5